99 Commits

Author SHA1 Message Date
joachimschmidt557
c2beaba85a stage2 ARM: fix callee_preserved_regs
Previously, the registers included r0, r1, r2, r3 which are not
included in the callee saved registers according to the Procedure Call
Standard for the ARM Architecture.
2021-02-09 23:57:43 +01:00
Andrew Kelley
102d954220
Merge pull request #7827 from Snektron/spirv-setup
Stage 2: SPIR-V setup
2021-02-01 12:49:51 -08:00
Andrew Kelley
1517ed0a5e
Merge pull request #7895 from Luukdegram/wasm-control-flow
stage2: wasm control flow
2021-02-01 12:29:22 -08:00
Veikka Tuominen
75acfcf0ea
stage2: reimplement switch 2021-02-01 15:45:11 +02:00
Veikka Tuominen
3ec5c9a3bc
stage2 cbe: implement not and some bitwise ops 2021-02-01 08:48:24 +02:00
Veikka Tuominen
106520329e
stage2 cbe: implement switchbr 2021-02-01 08:48:22 +02:00
Veikka Tuominen
258f3ec5ec
stage2 cbe: block results 2021-02-01 08:47:25 +02:00
Veikka Tuominen
bdfe3aeab8
stage2 cbe: condbr and breaks 2021-02-01 08:47:25 +02:00
Veikka Tuominen
6ca0ff90b6
stage2 cbe: use AutoIndentingStream 2021-02-01 08:47:25 +02:00
Veikka Tuominen
81c512f35b
stage2 cbe: loop instruction 2021-02-01 08:47:25 +02:00
Luuk de Gram
cc46c1b902
Add tests, fix locals that are created in blocks like loops, and handle all breaks correctly 2021-01-26 19:47:15 +01:00
Andrew Kelley
4ca1f4ec2e
Merge pull request #7846 from LemonBoy/filtertest
stage1: don't filter test blocks with empty label
2021-01-25 10:39:11 -08:00
Luuk de Gram
a0d81caec9
Nested conditions and loops support 2021-01-24 14:38:35 +01:00
Andrew Kelley
0d4b6ac741 add LTO support
The CLI gains -flto and -fno-lto options to override the default.
However, the cool thing about this is that the defaults are great! In
general when you use build-exe in release mode, Zig will enable LTO if
it would work and it would help.

zig cc supports detecting and honoring the -flto and -fno-lto flags as
well. The linkWithLld functions are improved to all be the same with
regards to copying the artifact instead of trying to pass single objects
through LLD with -r. There is possibly a future improvement here as
well; see the respective TODOs.

stage1 is updated to support outputting LLVM bitcode instead of machine
code when lto is enabled. This allows LLVM to optimize across the Zig and
C/C++ code boundary.

closes #2845
2021-01-23 18:18:07 -07:00
LemonBoy
134f5fd3d6 std: Update test "" to test where it makes sense 2021-01-22 15:46:58 +01:00
Robin Voetter
1055344673 SPIR-V: Use free list for result id generation 2021-01-19 15:28:17 +01:00
Robin Voetter
801732aebd SPIR-V: OpMemoryModel and basic capability generation 2021-01-19 15:28:17 +01:00
Robin Voetter
71ac82ecb0 SPIR-V: Make emitting binary more efficient 2021-01-19 15:28:17 +01:00
Robin Voetter
02c138fe70 SPIR-V: Add glsl450 and vulkan spir-v operating system definitions 2021-01-19 15:28:17 +01:00
Robin Voetter
b2b87b5900 SPIR-V: Linking and codegen setup 2021-01-19 15:28:17 +01:00
Robin Voetter
9a6babf482 SPIR-V: Add generated specification 2021-01-19 15:28:17 +01:00
Andrew Kelley
1a05b54520 update wasm backend to match new Module API
Fixes a logical merge conflict that I didn't notice before.
2021-01-18 14:12:05 -07:00
Andrew Kelley
46dd058d59
Merge pull request #7797 from Luukdegram/wasm-refactor
stage2: wasm - Refactor codegen for wasm similar to other backends
2021-01-18 12:35:52 -08:00
joachimschmidt557
ea6f3e3fd1
stage2 AArch64: add add/subtract (immediate) instructions 2021-01-17 22:40:14 +01:00
Jakub Konka
b25cf7db02 stage2 aarch64: add basic function pro/epilogue
Fix typo in `nop` implementation.
Simplify `aarch64` macOS tests.
2021-01-17 14:57:53 +01:00
Andrew Kelley
8c9ac4db97 stage2: implement error notes and regress -femit-zir
* Implement error notes
   - note: other symbol exported here
   - note: previous else prong is here
   - note: previous '_' prong is here
 * Add Compilation.CObject.ErrorMsg. This object properly converts to
   AllErrors.Message when the time comes.
 * Add Compilation.CObject.failure_retryable. Properly handles
   out-of-memory and other transient failures.
 * Introduce Module.SrcLoc which has not only a byte offset but also
   references the file which the byte offset applies to.
 * Scope.Block now contains both a pointer to the "owner" Decl and the
   "source" Decl. As an example, during inline function call, the
   "owner" will be the Decl of the caller and the "source" will be the
   Decl of the callee.
 * Module.ErrorMsg now sports a `file_scope` field so that notes can
   refer to source locations in a file other than the parent error
   message.
 * Some instances where a `*Scope` was stored, now store a
   `*Scope.Container`.
 * Some methods in the `Scope` namespace were moved to the more specific
   type, since there was only an implementation for one particular tag.
   - `removeDecl` moved to `Scope.Container`
   - `destroy` moved to `Scope.File`
 * Two kinds of Scope deleted:
   - zir_module
   - decl
 * astgen: properly use DeclVal / DeclRef. DeclVal was incorrectly
   changed to be a reference; this commit fixes it. Fewer ZIR
   instructions processed as a result.
   - declval_in_module is renamed to declval
   - previous declval ZIR instruction is deleted; it was only for .zir
     files.
 * Test harness: friendlier diagnostics when an unexpected set of errors
   is encountered.
 * zir_sema: fix analyzeInstBlockFlat by properly calling resolvingInst
   on the last zir instruction in the block.

Compile log implementation:
 * Write to a buffer rather than directly to stderr.
 * Only keep track of 1 callsite per Decl.
 * No longer mutate the ZIR Inst struct data.
 * "Compile log statement found" errors are only emitted when there are
   no other compile errors.

-femit-zir and support for .zir source files is regressed. If we wanted
to support this again, outputting .zir would need to be done as yet
another backend rather than in the haphazard way it was previously
implemented.

For parsing .zir, it was implemented previously in a way that was not
helpful for debugging. We need tighter integration with the test harness
for it to be useful; so clearly a rewrite is needed. Given that a
rewrite is needed, and it was getting in the way of progress and
organization of the rest of stage2, I regressed the feature.
2021-01-16 22:51:01 -07:00
joachimschmidt557
d2a297c2b3 stage2 ARM: add extra load/store instructions 2021-01-16 12:06:31 -08:00
joachimschmidt557
fbd5fbe729 stage2 AArch64: add very basic return values 2021-01-16 12:05:38 -08:00
Luuk de Gram
6a87ce0b62
Generate correct opcode for 'addGen' depending on type 2021-01-16 18:22:20 +01:00
Luuk de Gram
6c19aeddca
Add tests and move tests to wasm's own file 2021-01-16 14:58:04 +01:00
Luuk de Gram
4b2538f72c
Cleanup and 'add' instruction for bigger test area 2021-01-15 23:27:38 +01:00
Luuk de Gram
bb74f72e97
stage2: refactor wasm backend - similar to the other backends 2021-01-15 23:27:38 +01:00
Timon Kruiper
e1d8073d2f stage2: add support for loops in LLVM backend
A simple `while(true) {}` loop generates the following LLVMIR:
```
define i32 @main() {
Entry:
  br label %Loop

Loop:                                 ; preds = %Loop, %Entry
  br label %Loop
}
```

Also implement TZIR printing for loops and add a corresponding test.
2021-01-10 17:47:34 -08:00
Andrew Kelley
5c49a137d5
Merge pull request #7725 from FireFox317/even-more-llvm
stage2: initial implementation of control flow in LLVM backend + TZIR printing
2021-01-09 12:32:10 -08:00
Timon Kruiper
56c059077c stage2: add initial impl of control flow in LLVM backend
The following TZIR instrutions have been implemented in the backend:
- all cmp operators (lt, lte, gt, gte, eq, neq)
- block
- br
- condbr

The following LLVMIR is generated for a simple assert function:
```
define void @assert(i1 %0) {
Entry:
  %1 = alloca i1, align 1
  store i1 %0, i1* %1, align 1
  %2 = load i1, i1* %1, align 1
  %3 = xor i1 %2, true
  br i1 %3, label %Then, label %Else

Then:                                             ; preds = %Entry
  call void @llvm.debugtrap()
  unreachable

Else:                                             ; preds = %Entry
  br label %Block

Block:                                            ; preds = %Else
  ret void
}
```

See tests for more examples.
2021-01-08 19:30:52 +01:00
Jonathan Marler
31802c6c68 remove z/Z format specifiers
Zig's format system is flexible enough to add custom formatters.  This PR removes the new z/Z format specifiers that were added for printing Zig identifiers and replaces them with custom formatters.
2021-01-07 23:49:22 -08:00
Jay Petacat
a9b505fa77 Reduce use of deprecated IO types
Related: #4917
2021-01-07 23:48:58 -08:00
Andrew Kelley
76870a2265
Merge pull request #7700 from FireFox317/more-stage2-stuff-llvm
stage2: improvements to LLVM backend
2021-01-06 16:06:32 -08:00
Timon Kruiper
b1cfa923be stage2: rename and move files related to LLVM backend 2021-01-06 10:52:20 +01:00
Andrew Kelley
1a2dd85570 stage2: C backend: re-implement emit-h
and also mark functions as `extern "C"` as appropriate to support c++
compilers.
2021-01-05 17:41:14 -07:00
Andrew Kelley
cd95444e47 stage2: C backend: remove format() hackery
All C backend tests passing now, except for emit-h tests. Next task in
the branch is to restore emit-h.
2021-01-05 17:41:14 -07:00
Andrew Kelley
58cfaa5982 stage2: C backend: adjust spaces around functions 2021-01-05 17:41:14 -07:00
Andrew Kelley
7b8cede61f stage2: rework the C backend
* std.ArrayList gains `moveToUnmanaged` and dead code
   `ArrayListUnmanaged.appendWrite` is deleted.
 * emit_h state is attached to Module rather than Compilation.
 * remove the implementation of emit-h because it did not properly
   integrate with incremental compilation. I will re-implement it
   in a follow-up commit.
 * Compilation: use the .codegen_failure tag rather than
   .dependency_failure tag for when `bin_file.updateDecl` fails.

C backend:
 * Use a CValue tagged union instead of strings for C values.
 * Cleanly separate state into Object and DeclGen:
   - Object is present only when generating a .c file
   - DeclGen is present for both generating a .c and .h
 * Move some functions into their respective Object/DeclGen namespace.
 * Forward decls are managed by the incremental compilation frontend; C
   backend no longer renders function signatures based on callsites.
   For simplicity, all functions always get forward decls.
 * Constants are managed by the incremental compilation frontend. C
   backend no longer has a "constants" section.
 * Participate in incremental compilation. Each Decl gets an ArrayList
   for its generated C code and it is updated when the Decl is updated.
   During flush(), all these are joined together in the output file.
 * The new CValue tagged union is used to clean up using of assigning to
   locals without an additional pointer local.
 * Fix bug with bitcast of non-pointers making the memcpy destination
   immutable.
2021-01-05 17:41:14 -07:00
Andrew Kelley
006e7f6805 stage2: re-use ZIR for comptime and inline calls
Instead of freeing ZIR after semantic analysis, we keep it around so
that it can be used for comptime calls, inline calls, and generic
function calls. ZIR memory is now managed by the Decl arena.

Debug dump() functions are conditionally compiled; only available in
Debug builds of the compiler.

Add a test for an inline function call.
2021-01-02 19:11:55 -07:00
Andrew Kelley
9362f382ab stage2: implement function call inlining in the frontend
* remove the -Ddump-zir thing. that's handled through --verbose-ir
 * rework Fn to have an is_inline flag without requiring any more memory
   on the heap per function.
 * implement a rough first version of dumping typed zir (tzir) which is
   a lot more helpful for debugging than what we had before. We don't
   have a way to parse it though.
 * keep track of whether the inline-ness of a function changes because
   if it does we have to go update callsites.
 * add compile error for inline and export used together.

inline function calls and comptime function calls are implemented the
same way. A block instruction is set up to capture the result, and then
a scope is set up that has a flag for is_comptime and some state if the
scope is being inlined.

when analyzing `ret` instructions, zig looks for inlining state in the
scope, and if found, treats `ret` as a `break` instruction instead, with
the target block being the one set up at the inline callsite.

Follow-up items:
 * Complete out the debug TZIR dumping code.
 * Don't redundantly generate ZIR for each inline/comptime function
   call. Instead we should add a new state enum tag to Fn.
 * comptime and inlining branch quotas.
 * Add more test cases.
2021-01-02 19:11:19 -07:00
Andrew Kelley
974c008a0e convert more {} to {d} and {s} 2021-01-02 19:03:14 -07:00
LemonBoy
5b981b1be7 Remove some unwanted changes
Leftovers after a long rebase.
2021-01-02 17:12:58 -07:00
LemonBoy
1c13ca5a05 stage2: Use {s} instead of {} when formatting strings 2021-01-02 17:12:57 -07:00
joachimschmidt557
c5ec096b2f stage2 AArch64: add logical (shifted register) instructions 2021-01-01 14:43:12 -08:00
joachimschmidt557
c52ca0b178
stage2 ARM: implement genSetReg with compare_flags 2021-01-01 12:22:16 +01:00