142 Commits

Author SHA1 Message Date
Luuk de Gram
00b2e31589
Basic "Hello world" working 2021-04-08 22:47:08 +02:00
Andrew Kelley
9f744f19e7
Merge pull request #8464 from gracefuu/grace/wasm-ops
stage2 wasm: Add division and bitwise/boolean ops &, |, ^, and, or
2021-04-08 13:41:49 -07:00
joachimschmidt557
d7a89f9876 stage2 AArch64: Add conditional branch instructions 2021-04-08 13:39:11 -07:00
gracefu
e4a60b63f2
stage2 wasm: Add bitwise/boolean ops &, |, ^, and, or 2021-04-08 05:27:00 +08:00
gracefu
4c71942f84
stage2: Add .div to ir.zig 2021-04-08 05:26:56 +08:00
Andrew Kelley
015599d1ef C backend: enumerate all the types in renderType
Now that we're close to supporting all the types, get rid of the `else`
prong and explicitly list out those types that are not yet implemented.

Thanks @g-w1
2021-04-07 13:17:23 -07:00
Andrew Kelley
19cf987198 C backend: implement Enum types and values
They are lowered directly as the integer tag type, with no typedef.
2021-04-06 23:19:46 -07:00
gracefu
ec84742c89
stage2 wasm codegen: refactor to use wasm.buildOpcode 2021-04-05 16:19:52 +08:00
gracefu
3648e43dda
std/wasm: add buildOpcode to help construction of Opcodes 2021-04-05 14:44:00 +08:00
gracefu
869fc06c57
stage2 wasm: codegen mul op 2021-04-05 14:37:04 +08:00
gracefu
d1244d3608
stage2 wasm: codegen sub op 2021-04-05 14:37:04 +08:00
Andrew Kelley
545830c0ff LLVM sub-arch triple: remove TODO comment
See #6542 for more details. Upon investigation, this change is not
needed.
2021-04-04 16:10:54 -07:00
Andrew Kelley
97d7fddfb7 stage2: progress towards basic structs
Introduce `ResultLoc.none_or_ref` which is used by field access
expressions to avoid unnecessary loads when the field access itself
will do the load. This turns:

```zig
p.y - p.x - p.x
```

from

```zir
  %14 = load(%4) node_offset:8:12
  %15 = field_val(%14, "y") node_offset:8:13
  %16 = load(%4) node_offset:8:18
  %17 = field_val(%16, "x") node_offset:8:19
  %18 = sub(%15, %17) node_offset:8:16
  %19 = load(%4) node_offset:8:24
  %20 = field_val(%19, "x") node_offset:8:25
```

to

```zir
  %14 = field_val(%4, "y") node_offset:8:13
  %15 = field_val(%4, "x") node_offset:8:19
  %16 = sub(%14, %15) node_offset:8:16
  %17 = field_val(%4, "x") node_offset:8:25
```

Much more compact. This requires `Sema.zirFieldVal` to support both
pointers and non-pointers.

C backend: Implement typedefs for struct types, as well as the following
TZIR instructions:
 * mul
 * mulwrap
 * addwrap
 * subwrap
 * ref
 * struct_field_ptr

Note that add, addwrap, sub, subwrap, mul, mulwrap instructions are all
incorrect currently and need to be updated to properly handle wrapping
and non wrapping for signed and unsigned.

C backend: change indentation delta to 1, to make the output smaller and
to process fewer bytes.

I promise I will add a test case as soon as I fix those warnings that
are being printed for my test case.
2021-04-02 19:11:51 -07:00
joachimschmidt557
43d364afef stage2 AArch64: Add ldrh and ldrb instructions 2021-04-02 14:46:30 -07:00
Andrew Kelley
070a28e493
Merge pull request #8266 from ziglang/zir-memory-layout
rework ZIR memory layout; overhaul source locations
2021-03-31 23:11:15 -07:00
joachimschmidt557
e088a17f56 stage2 AArch64: implement strb and strh 2021-03-31 23:26:49 +02:00
Andrew Kelley
281a7baaea Merge remote-tracking branch 'origin/master' into zir-memory-layout
Wanted to make sure those new test cases still pass.

Also grab that CI fix so we can get those green check marks.
2021-03-28 19:42:43 -07:00
jacob gw
0005b34637 stage2: implement sema for @errorToInt and @intToError 2021-03-28 18:22:01 -07:00
Timon Kruiper
982df37135 stage2: handle void value in genRet in LLVM backend 2021-03-23 11:42:46 -07:00
Timon Kruiper
d73b0473a1 stage2: rename fail to todo in LLVM backend
This way we don't have to pass src to every function and we can simply
use the first node as the lazy source location for all the todo
errors.
2021-03-23 11:42:46 -07:00
Luuk de Gram
4b854b75d2
Fix getNot and add test cases 2021-03-22 19:56:38 +01:00
Luuk de Gram
803f9e5dd0
Implement more instructions for more control flow support 2021-03-22 19:56:35 +01:00
Timon Kruiper
a710368054 stage2: restructure LLVM backend
The LLVM backend is now structured into 3 different structs, namely
Object, DeclGen and FuncGen. Object represents an object that is
generated by the LLVM backend. DeclGen is responsible for generating
a decl and FuncGen is responsible for generating llvm instructions
from tzir in a function.
2021-03-20 15:10:44 -07:00
jacob gw
c50397c268 llvm backend: use new srcloc
this allows to compile with ninja
2021-03-19 14:46:37 -07:00
Andrew Kelley
bd2154da3d stage2: the code is compiling again
(with a lot of things commented out)
2021-03-18 22:48:28 -07:00
Andrew Kelley
b2682237db stage2: get Module and Sema compiling again
There are some `@panic("TODO")` in there but I'm trying to get the
branch to the point where collaborators can jump in.

Next is to repair the seam between LazySrcLoc and codegen's expected
absolute file offsets.
2021-03-18 22:19:28 -07:00
Jakub Konka
d484b3b3cb zld: use aarch64 for opcodes 2021-03-17 19:59:13 +01:00
Tadeo Kondrak
e8aa6f90d6
stage2 llvm bindings: use correct type for LLVMBool for ABI compat 2021-03-16 17:05:36 -06:00
Tadeo Kondrak
277b01a089
stage2 llvm bindings: rename LLVMBool to Bool 2021-03-14 22:32:26 -06:00
Veikka Tuominen
fc62ff77c3
stage2: error union payload must also be a valid variable type 2021-03-08 00:33:59 +02:00
jacob gw
30ffa052f2
stage2 cbe: add error union and error union operations 2021-03-08 00:33:59 +02:00
Veikka Tuominen
0a7be71bc2
stage2 cbe: non pointer optionals 2021-03-08 00:33:56 +02:00
Veikka Tuominen
cfc19eace7
stage2 cbe: errors 2021-03-08 00:33:07 +02:00
Veikka Tuominen
c22f010fdd
stage2 cbe: regular optional types 2021-03-08 00:33:07 +02:00
Veikka Tuominen
ca20d0ea26
stage2 cbe: pointer like optionals 2021-03-08 00:32:52 +02:00
Veikka Tuominen
8c6e7fb2c7
stage2: implement var args 2021-03-06 15:55:29 +02:00
Timon Kruiper
d4ec0279d3 stage2: add support for optionals in the LLVM backend
We can now codegen optionals! This includes the following instructions:
- is_null
- is_null_ptr
- is_non_null
- is_non_null_ptr
- optional_payload
- optional_payload_ptr
- br_void

Also includes a test for optionals.
2021-03-02 19:02:55 -07:00
Andrew Kelley
449f4de382 zig fmt src/ 2021-02-24 21:54:23 -07:00
Andrew Kelley
8e6c2b7a47 Merge remote-tracking branch 'origin/master' into ast-memory-layout 2021-02-24 15:08:23 -07:00
Veikka Tuominen
ef6aa3d027
Merge pull request #7960 from Luukdegram/wasm-extern
stage2: Add support for extern functions for the wasm backend
2021-02-21 12:22:01 +02:00
Isaac Freund
070e548acf
std: remove io.AutoIndentingStream
This type is not widely applicable enough to be a public part of the
public interface of the std.

The current implementation in only fully utilized by the zig fmt
implementation, which could benefit by even tighter integration as
will be demonstrated in the next commit. Therefore, move the current
io.AutoIndentingStream to lib/std/zig/render.zig.

The C backend of the self hosted compiler also use this type currently,
but it does not require anywhere near its full complexity. Therefore,
implement a greatly simplified version of this interface in
src/codegen/c.zig.
2021-02-16 23:20:46 +01:00
joachimschmidt557
c2beaba85a stage2 ARM: fix callee_preserved_regs
Previously, the registers included r0, r1, r2, r3 which are not
included in the callee saved registers according to the Procedure Call
Standard for the ARM Architecture.
2021-02-09 23:57:43 +01:00
Luuk de Gram
36df6a008f
Ensure function indices are correct and fix a memory leak 2021-02-05 18:06:25 +01:00
Luuk de Gram
aa3e0ff454
Create type declarations for extern functions and write the 'import' section 2021-02-05 18:06:20 +01:00
Andrew Kelley
102d954220
Merge pull request #7827 from Snektron/spirv-setup
Stage 2: SPIR-V setup
2021-02-01 12:49:51 -08:00
Andrew Kelley
1517ed0a5e
Merge pull request #7895 from Luukdegram/wasm-control-flow
stage2: wasm control flow
2021-02-01 12:29:22 -08:00
Veikka Tuominen
75acfcf0ea
stage2: reimplement switch 2021-02-01 15:45:11 +02:00
Veikka Tuominen
3ec5c9a3bc
stage2 cbe: implement not and some bitwise ops 2021-02-01 08:48:24 +02:00
Veikka Tuominen
106520329e
stage2 cbe: implement switchbr 2021-02-01 08:48:22 +02:00
Veikka Tuominen
258f3ec5ec
stage2 cbe: block results 2021-02-01 08:47:25 +02:00