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https://github.com/ziglang/zig.git
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stage2 AArch64: Add conditional branch instructions
This commit is contained in:
joachimschmidt557
Andrew Kelley
parent
ab5a445d25
commit
d7a89f9876
@ -200,7 +200,7 @@ test "FloatingPointRegister.toX" {
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/// Represents an instruction in the AArch64 instruction set
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pub const Instruction = union(enum) {
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MoveWideImmediate: packed struct {
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move_wide_immediate: packed struct {
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rd: u5,
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imm16: u16,
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hw: u2,
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@ -208,14 +208,14 @@ pub const Instruction = union(enum) {
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opc: u2,
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sf: u1,
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},
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PCRelativeAddress: packed struct {
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pc_relative_address: packed struct {
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rd: u5,
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immhi: u19,
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fixed: u5 = 0b10000,
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immlo: u2,
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op: u1,
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},
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LoadStoreRegister: packed struct {
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load_store_register: packed struct {
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rt: u5,
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rn: u5,
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offset: u12,
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@ -225,7 +225,7 @@ pub const Instruction = union(enum) {
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fixed: u3 = 0b111,
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size: u2,
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},
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LoadStorePairOfRegisters: packed struct {
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load_store_register_pair: packed struct {
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rt1: u5,
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rn: u5,
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rt2: u5,
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@ -235,20 +235,20 @@ pub const Instruction = union(enum) {
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fixed: u5 = 0b101_0_0,
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opc: u2,
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},
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LoadLiteral: packed struct {
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load_literal: packed struct {
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rt: u5,
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imm19: u19,
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fixed: u6 = 0b011_0_00,
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opc: u2,
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},
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ExceptionGeneration: packed struct {
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exception_generation: packed struct {
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ll: u2,
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op2: u3,
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imm16: u16,
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opc: u3,
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fixed: u8 = 0b1101_0100,
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},
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UnconditionalBranchRegister: packed struct {
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unconditional_branch_register: packed struct {
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op4: u5,
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rn: u5,
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op3: u6,
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@ -256,15 +256,15 @@ pub const Instruction = union(enum) {
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opc: u4,
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fixed: u7 = 0b1101_011,
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},
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UnconditionalBranchImmediate: packed struct {
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unconditional_branch_immediate: packed struct {
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imm26: u26,
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fixed: u5 = 0b00101,
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op: u1,
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},
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NoOperation: packed struct {
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no_operation: packed struct {
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fixed: u32 = 0b1101010100_0_00_011_0010_0000_000_11111,
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},
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LogicalShiftedRegister: packed struct {
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logical_shifted_register: packed struct {
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rd: u5,
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rn: u5,
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imm6: u6,
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@ -275,7 +275,7 @@ pub const Instruction = union(enum) {
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opc: u2,
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sf: u1,
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},
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AddSubtractImmediate: packed struct {
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add_subtract_immediate: packed struct {
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rd: u5,
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rn: u5,
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imm12: u12,
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@ -285,6 +285,20 @@ pub const Instruction = union(enum) {
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op: u1,
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sf: u1,
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},
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conditional_branch: struct {
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cond: u4,
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o0: u1,
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imm19: u19,
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o1: u1,
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fixed: u7 = 0b0101010,
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},
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compare_and_branch: struct {
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rt: u5,
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imm19: u19,
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op: u1,
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fixed: u6 = 0b011010,
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sf: u1,
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},
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pub const Shift = struct {
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shift: Type = .lsl,
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@ -303,19 +317,73 @@ pub const Instruction = union(enum) {
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};
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};
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pub const Condition = enum(u4) {
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/// Integer: Equal
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/// Floating point: Equal
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eq,
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/// Integer: Not equal
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/// Floating point: Not equal or unordered
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ne,
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/// Integer: Carry set
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/// Floating point: Greater than, equal, or unordered
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cs,
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/// Integer: Carry clear
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/// Floating point: Less than
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cc,
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/// Integer: Minus, negative
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/// Floating point: Less than
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mi,
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/// Integer: Plus, positive or zero
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/// Floating point: Greater than, equal, or unordered
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pl,
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/// Integer: Overflow
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/// Floating point: Unordered
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vs,
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/// Integer: No overflow
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/// Floating point: Ordered
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vc,
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/// Integer: Unsigned higher
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/// Floating point: Greater than, or unordered
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hi,
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/// Integer: Unsigned lower or same
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/// Floating point: Less than or equal
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ls,
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/// Integer: Signed greater than or equal
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/// Floating point: Greater than or equal
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ge,
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/// Integer: Signed less than
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/// Floating point: Less than, or unordered
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lt,
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/// Integer: Signed greater than
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/// Floating point: Greater than
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gt,
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/// Integer: Signed less than or equal
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/// Floating point: Less than, equal, or unordered
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le,
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/// Integer: Always
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/// Floating point: Always
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al,
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/// Integer: Always
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/// Floating point: Always
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nv,
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};
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pub fn toU32(self: Instruction) u32 {
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return switch (self) {
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.MoveWideImmediate => |v| @bitCast(u32, v),
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.PCRelativeAddress => |v| @bitCast(u32, v),
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.LoadStoreRegister => |v| @bitCast(u32, v),
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.LoadStorePairOfRegisters => |v| @bitCast(u32, v),
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.LoadLiteral => |v| @bitCast(u32, v),
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.ExceptionGeneration => |v| @bitCast(u32, v),
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.UnconditionalBranchRegister => |v| @bitCast(u32, v),
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.UnconditionalBranchImmediate => |v| @bitCast(u32, v),
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.NoOperation => |v| @bitCast(u32, v),
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.LogicalShiftedRegister => |v| @bitCast(u32, v),
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.AddSubtractImmediate => |v| @bitCast(u32, v),
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.move_wide_immediate => |v| @bitCast(u32, v),
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.pc_relative_address => |v| @bitCast(u32, v),
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.load_store_register => |v| @bitCast(u32, v),
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.load_store_register_pair => |v| @bitCast(u32, v),
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.load_literal => |v| @bitCast(u32, v),
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.exception_generation => |v| @bitCast(u32, v),
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.unconditional_branch_register => |v| @bitCast(u32, v),
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.unconditional_branch_immediate => |v| @bitCast(u32, v),
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.no_operation => |v| @bitCast(u32, v),
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.logical_shifted_register => |v| @bitCast(u32, v),
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.add_subtract_immediate => |v| @bitCast(u32, v),
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// TODO once packed structs work, this can be refactored
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.conditional_branch => |v| @as(u32, v.cond) | (@as(u32, v.o0) << 4) | (@as(u32, v.imm19) << 5) | (@as(u32, v.o1) << 24) | (@as(u32, v.fixed) << 25),
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.compare_and_branch => |v| @as(u32, v.rt) | (@as(u32, v.imm19) << 5) | (@as(u32, v.op) << 24) | (@as(u32, v.fixed) << 25) | (@as(u32, v.sf) << 31),
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};
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}
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@ -329,7 +397,7 @@ pub const Instruction = union(enum) {
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32 => {
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assert(shift % 16 == 0 and shift <= 16);
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return Instruction{
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.MoveWideImmediate = .{
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.move_wide_immediate = .{
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.rd = rd.id(),
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.imm16 = imm16,
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.hw = @intCast(u2, shift / 16),
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@ -341,7 +409,7 @@ pub const Instruction = union(enum) {
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64 => {
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assert(shift % 16 == 0 and shift <= 48);
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return Instruction{
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.MoveWideImmediate = .{
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.move_wide_immediate = .{
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.rd = rd.id(),
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.imm16 = imm16,
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.hw = @intCast(u2, shift / 16),
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@ -358,7 +426,7 @@ pub const Instruction = union(enum) {
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assert(rd.size() == 64);
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const imm21_u = @bitCast(u21, imm21);
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return Instruction{
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.PCRelativeAddress = .{
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.pc_relative_address = .{
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.rd = rd.id(),
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.immlo = @truncate(u2, imm21_u),
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.immhi = @truncate(u19, imm21_u >> 2),
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@ -522,7 +590,7 @@ pub const Instruction = union(enum) {
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.str, .strh, .strb => 0b00,
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};
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return Instruction{
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.LoadStoreRegister = .{
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.load_store_register = .{
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.rt = rt.id(),
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.rn = rn.id(),
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.offset = off,
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@ -544,7 +612,7 @@ pub const Instruction = union(enum) {
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};
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}
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fn loadStorePairOfRegisters(
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fn loadStoreRegisterPair(
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rt1: Register,
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rt2: Register,
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rn: Register,
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@ -557,7 +625,7 @@ pub const Instruction = union(enum) {
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assert(-256 <= offset and offset <= 252);
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const imm7 = @truncate(u7, @bitCast(u9, offset >> 2));
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return Instruction{
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.LoadStorePairOfRegisters = .{
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.load_store_register_pair = .{
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.rt1 = rt1.id(),
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.rn = rn.id(),
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.rt2 = rt2.id(),
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@ -572,7 +640,7 @@ pub const Instruction = union(enum) {
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assert(-512 <= offset and offset <= 504);
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const imm7 = @truncate(u7, @bitCast(u9, offset >> 3));
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return Instruction{
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.LoadStorePairOfRegisters = .{
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.load_store_register_pair = .{
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.rt1 = rt1.id(),
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.rn = rn.id(),
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.rt2 = rt2.id(),
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@ -591,7 +659,7 @@ pub const Instruction = union(enum) {
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switch (rt.size()) {
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32 => {
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return Instruction{
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.LoadLiteral = .{
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.load_literal = .{
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.rt = rt.id(),
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.imm19 = imm19,
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.opc = 0b00,
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@ -600,7 +668,7 @@ pub const Instruction = union(enum) {
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},
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64 => {
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return Instruction{
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.LoadLiteral = .{
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.load_literal = .{
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.rt = rt.id(),
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.imm19 = imm19,
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.opc = 0b01,
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@ -618,7 +686,7 @@ pub const Instruction = union(enum) {
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imm16: u16,
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) Instruction {
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return Instruction{
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.ExceptionGeneration = .{
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.exception_generation = .{
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.ll = ll,
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.op2 = op2,
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.imm16 = imm16,
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@ -637,7 +705,7 @@ pub const Instruction = union(enum) {
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assert(rn.size() == 64);
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return Instruction{
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.UnconditionalBranchRegister = .{
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.unconditional_branch_register = .{
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.op4 = op4,
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.rn = rn.id(),
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.op3 = op3,
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@ -652,7 +720,7 @@ pub const Instruction = union(enum) {
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offset: i28,
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) Instruction {
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return Instruction{
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.UnconditionalBranchImmediate = .{
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.unconditional_branch_immediate = .{
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.imm26 = @bitCast(u26, @intCast(i26, offset >> 2)),
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.op = op,
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},
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@ -671,7 +739,7 @@ pub const Instruction = union(enum) {
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32 => {
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assert(shift.amount < 32);
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return Instruction{
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.LogicalShiftedRegister = .{
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.logical_shifted_register = .{
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.rd = rd.id(),
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.rn = rn.id(),
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.imm6 = shift.amount,
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@ -685,7 +753,7 @@ pub const Instruction = union(enum) {
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},
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64 => {
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return Instruction{
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.LogicalShiftedRegister = .{
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.logical_shifted_register = .{
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.rd = rd.id(),
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.rn = rn.id(),
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.imm6 = shift.amount,
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@ -710,7 +778,7 @@ pub const Instruction = union(enum) {
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shift: bool,
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) Instruction {
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return Instruction{
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.AddSubtractImmediate = .{
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.add_subtract_immediate = .{
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.rd = rd.id(),
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.rn = rn.id(),
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.imm12 = imm12,
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@ -726,6 +794,43 @@ pub const Instruction = union(enum) {
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};
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}
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fn conditionalBranch(
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o0: u1,
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o1: u1,
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cond: Condition,
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offset: i21,
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) Instruction {
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assert(offset & 0b11 == 0b00);
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return Instruction{
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.conditional_branch = .{
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.cond = @enumToInt(cond),
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.o0 = o0,
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.imm19 = @bitCast(u19, @intCast(i19, offset >> 2)),
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.o1 = o1,
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},
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};
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}
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fn compareAndBranch(
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op: u1,
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rt: Register,
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offset: i21,
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) Instruction {
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assert(offset & 0b11 == 0b00);
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return Instruction{
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.compare_and_branch = .{
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.rt = rt.id(),
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.imm19 = @bitCast(u19, @intCast(i19, offset >> 2)),
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.op = op,
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.sf = switch (rt.size()) {
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32 => 0b0,
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64 => 0b1,
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else => unreachable, // unexpected register size
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},
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},
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};
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}
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// Helper functions for assembly syntax functions
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// Move wide (immediate)
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@ -821,19 +926,19 @@ pub const Instruction = union(enum) {
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};
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pub fn ldp(rt1: Register, rt2: Register, rn: Register, offset: LoadStorePairOffset) Instruction {
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return loadStorePairOfRegisters(rt1, rt2, rn, offset.offset, @enumToInt(offset.encoding), true);
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return loadStoreRegisterPair(rt1, rt2, rn, offset.offset, @enumToInt(offset.encoding), true);
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}
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pub fn ldnp(rt1: Register, rt2: Register, rn: Register, offset: i9) Instruction {
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return loadStorePairOfRegisters(rt1, rt2, rn, offset, 0, true);
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return loadStoreRegisterPair(rt1, rt2, rn, offset, 0, true);
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}
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pub fn stp(rt1: Register, rt2: Register, rn: Register, offset: LoadStorePairOffset) Instruction {
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return loadStorePairOfRegisters(rt1, rt2, rn, offset.offset, @enumToInt(offset.encoding), false);
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return loadStoreRegisterPair(rt1, rt2, rn, offset.offset, @enumToInt(offset.encoding), false);
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}
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pub fn stnp(rt1: Register, rt2: Register, rn: Register, offset: i9) Instruction {
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return loadStorePairOfRegisters(rt1, rt2, rn, offset, 0, false);
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return loadStoreRegisterPair(rt1, rt2, rn, offset, 0, false);
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}
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// Exception generation
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@ -885,7 +990,7 @@ pub const Instruction = union(enum) {
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// Nop
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pub fn nop() Instruction {
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return Instruction{ .NoOperation = .{} };
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return Instruction{ .no_operation = .{} };
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}
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// Logical (shifted register)
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@ -939,6 +1044,22 @@ pub const Instruction = union(enum) {
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pub fn subs(rd: Register, rn: Register, imm: u12, shift: bool) Instruction {
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return addSubtractImmediate(0b1, 0b1, rd, rn, imm, shift);
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}
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// Conditional branch
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pub fn bCond(cond: Condition, offset: i21) Instruction {
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return conditionalBranch(0b0, 0b0, cond, offset);
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}
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// Compare and branch
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pub fn cbz(rt: Register, offset: i21) Instruction {
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return compareAndBranch(0b0, rt, offset);
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}
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pub fn cbnz(rt: Register, offset: i21) Instruction {
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return compareAndBranch(0b1, rt, offset);
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}
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};
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test {
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@ -1092,6 +1213,14 @@ test "serialize instructions" {
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.inst = Instruction.subs(.x0, .x5, 11, true),
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.expected = 0b1_1_1_100010_1_0000_0000_1011_00101_00000,
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},
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.{ // b.hi #-4
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.inst = Instruction.bCond(.hi, -4),
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.expected = 0b0101010_0_1111111111111111111_0_1000,
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},
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.{ // cbz x10, #40
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.inst = Instruction.cbz(.x10, 40),
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.expected = 0b1_011010_0_0000000000000001010_01010,
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},
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};
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for (testcases) |case| {
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@ -1256,7 +1256,7 @@ pub fn updateDecl(self: *MachO, module: *Module, decl: *Module.Decl) !void {
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const inst = code_buffer.items[fixup.offset..][0..4];
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var parsed = mem.bytesAsValue(meta.TagPayload(
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aarch64.Instruction,
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aarch64.Instruction.PCRelativeAddress,
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aarch64.Instruction.pc_relative_address,
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), inst);
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const this_page = @intCast(i32, this_addr >> 12);
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const target_page = @intCast(i32, target_addr >> 12);
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@ -1268,7 +1268,7 @@ pub fn updateDecl(self: *MachO, module: *Module, decl: *Module.Decl) !void {
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const inst = code_buffer.items[fixup.offset + 4 ..][0..4];
|
||||
var parsed = mem.bytesAsValue(meta.TagPayload(
|
||||
aarch64.Instruction,
|
||||
aarch64.Instruction.LoadStoreRegister,
|
||||
aarch64.Instruction.load_store_register,
|
||||
), inst);
|
||||
const narrowed = @truncate(u12, target_addr);
|
||||
const offset = try math.divExact(u12, narrowed, 8);
|
||||
|
||||
@ -1668,7 +1668,7 @@ fn doRelocs(self: *Zld) !void {
|
||||
var parsed = mem.bytesAsValue(
|
||||
meta.TagPayload(
|
||||
aarch64.Instruction,
|
||||
aarch64.Instruction.UnconditionalBranchImmediate,
|
||||
aarch64.Instruction.unconditional_branch_immediate,
|
||||
),
|
||||
inst,
|
||||
);
|
||||
@ -1688,7 +1688,7 @@ fn doRelocs(self: *Zld) !void {
|
||||
var parsed = mem.bytesAsValue(
|
||||
meta.TagPayload(
|
||||
aarch64.Instruction,
|
||||
aarch64.Instruction.PCRelativeAddress,
|
||||
aarch64.Instruction.pc_relative_address,
|
||||
),
|
||||
inst,
|
||||
);
|
||||
@ -1706,7 +1706,7 @@ fn doRelocs(self: *Zld) !void {
|
||||
var parsed = mem.bytesAsValue(
|
||||
meta.TagPayload(
|
||||
aarch64.Instruction,
|
||||
aarch64.Instruction.AddSubtractImmediate,
|
||||
aarch64.Instruction.add_subtract_immediate,
|
||||
),
|
||||
inst,
|
||||
);
|
||||
@ -1719,7 +1719,7 @@ fn doRelocs(self: *Zld) !void {
|
||||
var parsed = mem.bytesAsValue(
|
||||
meta.TagPayload(
|
||||
aarch64.Instruction,
|
||||
aarch64.Instruction.LoadStoreRegister,
|
||||
aarch64.Instruction.load_store_register,
|
||||
),
|
||||
inst,
|
||||
);
|
||||
@ -1774,7 +1774,7 @@ fn doRelocs(self: *Zld) !void {
|
||||
const curr = mem.bytesAsValue(
|
||||
meta.TagPayload(
|
||||
aarch64.Instruction,
|
||||
aarch64.Instruction.AddSubtractImmediate,
|
||||
aarch64.Instruction.add_subtract_immediate,
|
||||
),
|
||||
inst,
|
||||
);
|
||||
@ -1783,7 +1783,7 @@ fn doRelocs(self: *Zld) !void {
|
||||
const curr = mem.bytesAsValue(
|
||||
meta.TagPayload(
|
||||
aarch64.Instruction,
|
||||
aarch64.Instruction.LoadStoreRegister,
|
||||
aarch64.Instruction.load_store_register,
|
||||
),
|
||||
inst,
|
||||
);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user