87 Commits

Author SHA1 Message Date
Andrew Kelley
62f54aa39c Sema: in-memory coercion of differently named int types
which have the same number of bits and the same signedness.
2022-04-06 02:39:55 -07:00
Andrew Kelley
51ef31a833 Sema: add empty tuple to mutable slice coercion 2022-04-04 14:29:08 -07:00
Andrew Kelley
05947ea870 stage2: implement @intToError with safety
This commit introduces a new AIR instruction `cmp_lt_errors_len`. It's
specific to this use case for two reasons:

 * The total number of errors is not stable during semantic analysis; it
   can only be reliably checked when flush() is called. So the backend
   that is lowering the instruction must emit a relocation of some kind
   and then populate it during flush().
 * The fewer AIR instructions in memory, the better for compiler
   performance, so we squish complex meanings into AIR tags without
   hesitation.

The instruction is implemented only in the LLVM backend so far. It does
this by creating a simple function which is gutted and re-populated
with each flush().

AstGen now uses ResultLoc.coerced_ty for `@intToError` and Sema does the
coercion.
2022-03-29 22:19:06 -07:00
Andrew Kelley
b59428e9f7 Sema: adjust coercion of undefined error union payload
To no longer set the error code to undefined. This fixes the problem
where an undefined single-item pointer coerced to an error union of a
slice set the whole thing to undefined even though the sub-coercion to
the slice would have produced a defined value.
2022-03-29 16:56:12 -07:00
Veikka Tuominen
c517e65d8f Sema: implement coerceInMemoryAllowed for optionals 2022-03-28 13:05:40 -07:00
Andrew Kelley
74ccd0c40b Sema: Value.copy: we gotta copy the bytes
For Value.Tag.bytes, the value copy implementation did not copy the
bytes array. No good. This operation must do a deep copy. If we want
some other mechanism for not copying very large byte buffers then it has
to work differently than this one.
2022-03-23 19:20:38 -07:00
Luuk de Gram
5cb16dfa59
wasm: Enable all passing tests
All tests have been manually verified which are now passing. This means that any remaining
TODO is an actual to-be-fixed or to-be-implemented test case.
2022-03-23 21:40:33 +01:00
Mitchell Hashimoto
91fd0f42c8 stage2: out of bounds error for slicing 2022-03-21 22:10:34 -04:00
Jakub Konka
d71bd0300b
Merge pull request #11195 from mparadinha/float-to-int
stage2: x86_64: implement `@floatToInt` for `f32` and `f64`
2022-03-21 23:54:36 +01:00
mparadinha
355d0d0e7e stage2: x86_64: floatToInt for f32 and f64 2022-03-16 21:27:50 +00:00
joachimschmidt557
dcc1de12b0
stage2 ARM: implement addwrap, subwrap, mulwrap 2022-03-16 20:20:07 +01:00
joachimschmidt557
ca1ffb0951
stage2 ARM: genSetStack for stack_argument_offset 2022-03-16 20:19:58 +01:00
Andrew Kelley
2f92d1a026 stage2: fixups for topolarity-comptime-memory-reinterp branch
* don't store `has_well_defined_layout` in memory.
 * remove struct `hasWellDefinedLayout` logic. it's just
   `layout != .Auto`. This means we only need one implementation, in
   Type.
 * fix some of the cases being wrong in `hasWellDefinedLayout`, such as
   optional pointers.
 * move `tag_ty_inferred` field into a position that makes it more
   obvious how the struct layout will be done. Also we don't have a
   compiler that intelligently moves fields around so this layout is
   better.
 * Sema: don't `resolveTypeLayout` in `zirCoerceResultPtr` unless
   necessary.
 * Rename `ComptimePtrLoadKit` `target` field to `pointee` to avoid
   confusion with `target`.
2022-03-14 21:43:03 -07:00
Cody Tapscott
1f76b4c6b8 stage2 llvm: Respect container type when lowering parent pointers
We need to make sure that we bitcast our pointers correctly before
we use get_element_ptr to compute the offset for the parent
pointer.

This also includes a small fix-up for a problem where ptrs to const
i64/u64 were not using the correct type in >1-level decl chains
(where we call lowerParentPtr recursively)
2022-03-14 21:42:43 -07:00
Andrew Kelley
b2a1b4c085 Sema: improve lowering of stores to bitcasted vector pointers
Detect if we are storing an array operand to a bitcasted vector pointer.
If so, we instead reach through the bitcasted pointer to the vector pointer,
bitcast the array operand to a vector, and then lower this as a store of
a vector value to a vector pointer. This generally results in better code,
as well as working around an LLVM bug.

See #11154
2022-03-14 00:11:46 -07:00
Mitchell Hashimoto
569870ca41 stage2: error_set_merged type equality
This implements type equality for error sets. This is done
through element-wise error set comparison.

Inferred error sets are always distinct types and other error sets are
always sorted. See #11022.
2022-03-10 14:20:16 -07:00
joachimschmidt557
95fc41b2b4 stage2 ARM: implement ret_load 2022-03-08 21:10:04 +01:00
Mitchell Hashimoto
55ccf4c7a8 stage2: elem vals of many pointers need not deref pointers
By the time zirElemVal is reached for a many pointer, a load has already
happened, making sure the operand is already dereferenced.

This makes `mem.sliceTo` now work.
2022-03-08 14:10:43 -05:00
Jakub Konka
404f5d6179 x64: pass more behavior/cast.zig tests 2022-03-08 10:56:54 +01:00
joachimschmidt557
3ea603c82a stage2 ARM: implement ptr_add, ptr_sub for all element sizes
Also reduces slice_elem_val to ptr_add, simplifying the implementation
2022-03-08 10:54:08 +01:00
Luuk de Gram
70fc6e3776
wasm: call into generateSymbol when lowering
This also unifies the wasm backend to use `generateSymbol` when lowering a constant
that cannot be lowered to an immediate value.
As both decls and constants are now refactored, the old `genTypedValue` is removed.
2022-03-06 19:38:53 +01:00
Luuk de Gram
5a45fe2dba
wasm: Call generateSymbol for updateDecl
To unify the wasm backend with the other backends, we will now call `generateSymbol` to
lower a Decl into bytes. This means we also have to change some function signatures
to comply with the linker interface.

Since the general purpose generateSymbol is less featureful than wasm's, some tests are
temporarily disabled.
2022-03-06 19:38:50 +01:00
joachimschmidt557
a06e9eca45
stage2 AArch64: add more slice support
* airSlice
* airArrayToSlice
* and initial support for airSlicePtr and co
2022-03-05 11:31:51 +01:00
joachimschmidt557
d486a7b811 stage2 ARM: generate less no-op branches
The checks detecting such no-op branches (essentially instructions
that branch to the instruction immediately following the branch) were
tightened to catch more of these occurrences.
2022-03-04 23:28:14 +01:00
Mitchell Hashimoto
b96d5fd71f
stage2: peer resolve const array pointer to unknown ptr 2022-03-03 11:08:14 -08:00
Mitchell Hashimoto
0924f17a23
stage2: peer resolve const u8 slices correctly 2022-03-03 11:04:04 -08:00
Andrew Kelley
1c8a86f063 Sema: detect comptime-known union initializations
Follow a similar pattern as we already do for validate_array_init and
validate_struct_init.

I threw in a bit of behavior test cleanup on top of it.
2022-03-02 17:28:39 -07:00
Jakub Konka
77072d1a17 x64: fix bug in lowering optionals directly to immediate 2022-03-02 17:40:37 +01:00
Jakub Konka
c9d1db7e8e x64: fix incorrect calc of rdi spill stack loc for backpatching 2022-03-02 14:53:02 +01:00
Jakub Konka
350bf9db13 x64: fix intCast to properly clear out dest register 2022-03-02 14:34:43 +01:00
Jakub Konka
d35cae551e x64: rectify and add missing optionals bits
Includes changes/additions to:
* `wrap_optional`
* `optional_payload`
* `isNull` helper
2022-03-02 14:05:29 +01:00
Jakub Konka
52205a3c16 x64: fix array to slice impl 2022-03-01 17:59:39 +01:00
Jakub Konka
ec54ceee6d
Merge pull request #11016 from ziglang/x64-more-codegen 2022-03-01 09:14:23 +01:00
Andrew Kelley
4763fd1a41 Sema: clean up peer resolution of errors
* Fix compile error for `zirErrorUnionType`.
 * Convert zirMergeErrorSets logic to call `Type.errorSetMerge`.
   It does not need to create a Decl as the TODO comment hinted.
 * Extract out a function called `resolveInferredErrorSetTy`.
 * Rework `resolvePeerTypes` with respect to error unions and
   error sets. This is a less complex implementation that passes all the
   same tests and uses many fewer lines of code by taking advantage of
   the function `coerceInMemoryAllowedErrorSets`.
   - Always merge error sets in the order that makes sense, even when
     that means `@typeInfo` incompatibility with stage1.
 * `Type.errorSetMerge` no longer overallocates.
 * Don't skip passing tests.
2022-02-28 23:15:58 -07:00
Mitchell Hashimoto
ea00e50045 stage2: skip error union test on native 2022-02-28 20:42:13 -07:00
Mitchell Hashimoto
0eb3cb9e8c stage2: order of error set merging should match stage1 2022-02-28 20:42:13 -07:00
Mitchell Hashimoto
6dae1de017 skip tests on native backends 2022-02-28 20:42:13 -07:00
Mitchell Hashimoto
b4ce855788 stage2: error union and non-error set/union peer cast resolution 2022-02-28 20:42:13 -07:00
Mitchell Hashimoto
38aae2cb7c stage2: peer resolve error sets and unions, add more tests 2022-02-28 20:42:13 -07:00
Jakub Konka
cfbc3537ef x64: pass more behavior tests 2022-02-28 23:20:05 +01:00
Mitchell Hashimoto
a7ca40b281 stage2: sentinel comp during peer type resolution should use elem type
We were using the array type, not the element type. Also, we should do
the sentinel comparison after we verify that the element types of both
are compatible.
2022-02-28 16:27:16 -05:00
joachimschmidt557
1bf8da19e1
stage2 ARM: implement slice and array_to_slice 2022-02-27 21:38:56 +01:00
joachimschmidt557
91fbcf7093
stage2 ARM: enable more behavior tests 2022-02-27 21:38:56 +01:00
Andrew Kelley
e81b21a0ea
Merge pull request #10992 from mitchellh/peer-slices
stage2: peer resolve *[N]T to []T and E![]T and [*]T, handle in-memory coercion
2022-02-26 18:49:44 -05:00
Mitchell Hashimoto
156316bc7c
stage2: skip more tests for native backends 2022-02-26 13:56:50 -08:00
Veikka Tuominen
ee149aaa03 stage2: actually coerce in coerce_result_ptr at comptime 2022-02-26 12:51:23 -07:00
Mitchell Hashimoto
f0232fc07d
stage2: split up the big sentinel peer cast test to multiple
This way we can fix them one at a time.
2022-02-25 18:56:27 -08:00
Mitchell Hashimoto
943ee59bb1
stage2: *[N]T to [*]T (and vice versa) 2022-02-25 17:29:50 -08:00
Mitchell Hashimoto
e442f88b76
stage2: add other backend skips until they determine they pass 2022-02-25 17:03:49 -08:00
Mitchell Hashimoto
bcf3eb5663
stage2: another passing test 2022-02-25 13:35:36 -08:00