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x64: fix incorrect calc of rdi spill stack loc for backpatching

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This commit is contained in:
Jakub Konka 2022-03-02 14:53:02 +01:00
parent 350bf9db13
commit c9d1db7e8e
2 changed files with 7 additions and 2 deletions
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7
src/arch/x86_64/CodeGen.zig
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@ -472,10 +472,14 @@ fn gen(self: *Self) InnerError!void {
.regs = 0,
.disp = mem.alignForwardGeneric(u32, self.next_stack_offset, 8),
};
var disp = data.disp + 8;
inline for (callee_preserved_regs) |reg, i| {
if (self.register_manager.isRegAllocated(reg)) {
if (reg.to64() == .rdi) {
for (self.ret_backpatches.items) |inst| {
log.debug(".rdi was spilled, backpatching with mov from stack at offset {}", .{
-@intCast(i32, disp),
});
const ops = Mir.Ops.decode(self.mir_instructions.items(.ops)[inst]);
self.mir_instructions.set(inst, Mir.Inst{
.tag = .mov,
@ -484,12 +488,13 @@ fn gen(self: *Self) InnerError!void {
.reg2 = .rbp,
.flags = 0b01,
}).encode(),
.data = .{ .imm = @bitCast(u32, -@intCast(i32, self.max_end_stack + 8)) },
.data = .{ .imm = @bitCast(u32, -@intCast(i32, disp)) },
});
}
}
data.regs |= 1 << @intCast(u5, i);
self.max_end_stack += 8;
disp += 8;
}
}
break :blk try self.addExtra(data);

2
test/behavior/cast.zig
View File

@ -19,7 +19,7 @@ test "integer literal to pointer cast" {
test "peer type resolution: ?T and T" {
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_x86_64 or builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
try expect(peerTypeTAndOptionalT(true, false).? == 0);
try expect(peerTypeTAndOptionalT(false, false).? == 3);