From c9d1db7e8eda6374bfc5ba51097e24d93ab91ddb Mon Sep 17 00:00:00 2001
From: Jakub Konka <kubkon@jakubkonka.com>
Date: Wed, 2 Mar 2022 14:53:02 +0100
Subject: [PATCH] x64: fix incorrect calc of rdi spill stack loc for
 backpatching

---
 src/arch/x86_64/CodeGen.zig | 7 ++++++-
 test/behavior/cast.zig      | 2 +-
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/arch/x86_64/CodeGen.zig b/src/arch/x86_64/CodeGen.zig
index 8efb1042ef..da98c1c901 100644
--- a/src/arch/x86_64/CodeGen.zig
+++ b/src/arch/x86_64/CodeGen.zig
@@ -472,10 +472,14 @@ fn gen(self: *Self) InnerError!void {
                 .regs = 0,
                 .disp = mem.alignForwardGeneric(u32, self.next_stack_offset, 8),
             };
+            var disp = data.disp + 8;
             inline for (callee_preserved_regs) |reg, i| {
                 if (self.register_manager.isRegAllocated(reg)) {
                     if (reg.to64() == .rdi) {
                         for (self.ret_backpatches.items) |inst| {
+                            log.debug(".rdi was spilled, backpatching with mov from stack at offset {}", .{
+                                -@intCast(i32, disp),
+                            });
                             const ops = Mir.Ops.decode(self.mir_instructions.items(.ops)[inst]);
                             self.mir_instructions.set(inst, Mir.Inst{
                                 .tag = .mov,
@@ -484,12 +488,13 @@ fn gen(self: *Self) InnerError!void {
                                     .reg2 = .rbp,
                                     .flags = 0b01,
                                 }).encode(),
-                                .data = .{ .imm = @bitCast(u32, -@intCast(i32, self.max_end_stack + 8)) },
+                                .data = .{ .imm = @bitCast(u32, -@intCast(i32, disp)) },
                             });
                         }
                     }
                     data.regs |= 1 << @intCast(u5, i);
                     self.max_end_stack += 8;
+                    disp += 8;
                 }
             }
             break :blk try self.addExtra(data);
diff --git a/test/behavior/cast.zig b/test/behavior/cast.zig
index 30c3e12ce0..9bdb0f35f6 100644
--- a/test/behavior/cast.zig
+++ b/test/behavior/cast.zig
@@ -19,7 +19,7 @@ test "integer literal to pointer cast" {
 
 test "peer type resolution: ?T and T" {
     if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
-    if (builtin.zig_backend == .stage2_x86_64 or builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
+    if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
 
     try expect(peerTypeTAndOptionalT(true, false).? == 0);
     try expect(peerTypeTAndOptionalT(false, false).? == 3);