1226 Commits

Author SHA1 Message Date
Andrew Kelley
b0995cb9f9 stage2: correct logic for analyzeIsNull 2020-08-26 19:53:36 -07:00
Vexu
cc26cb9b23 stage2: codegen needed for basic for loop 2020-08-26 19:50:56 -07:00
Vexu
fb28349349 stage2: astgen catch 2020-08-26 19:50:56 -07:00
Vexu
bf014d529a stage2: array access astgen 2020-08-26 19:50:56 -07:00
Vexu
bcd04089eb stage2: add helpful error message for invalid for operands 2020-08-26 19:50:56 -07:00
Vexu
b1aa2857ff stage2: astgen for loops 2020-08-26 19:50:56 -07:00
Andrew Kelley
0c5faa61ae stage2: codegen: fix reuseOperand not doing death bookkeeping 2020-08-26 01:00:04 -07:00
Andrew Kelley
237d9a105d stage2: support debug dumping zir as a build option
So that it's not needed to manually comment and uncomment the debug
code.
2020-08-25 22:44:18 -07:00
Andrew Kelley
e97157f71c stage2: codegen for conditional branching
* Move branch-local register and stack allocation metadata to the
   function-local struct. Conditional branches clone this data in order
   to restore it after generating machine code for a branch.
   Branch-local data is now only the instruction table mapping *ir.Inst
   to MCValue.
 * Implement conditional branching
   - Process operand deaths
   - Handle register and stack allocation metadata
 * Avoid storing unreferenced or void typed instructions into
   the branch-local instruction table.
 * Fix integer types reporting the wrong value for hasCodeGenBits.
 * Remove the codegen optimization for eliding length-0 jumps. I need to
   reexamine how this works because it was causing invalid jumps to be
   emitted.
2020-08-25 22:44:18 -07:00
Andrew Kelley
b68fa9970b stage2 codegen: Rework genCondBr
so that the arch-independent logic isn't buried and duplicated.
2020-08-25 22:44:18 -07:00
Jakub Konka
982ab7df6c
Merge pull request #6161 from kubkon/macho-text
Add (empty) __TEXT segment load command
2020-08-26 07:03:58 +02:00
Jakub Konka
55dc81ba2a
Hardcode runtime (libSystem) version to minimum possible
While we try to work out what the correlation between the OS and runtime
versions is, this commit hardcodes the latter to the minimum (compat)
version of 1.0.0.

Signed-off-by: Jakub Konka <kubkon@jakubkonka.com>
2020-08-26 06:30:54 +02:00
Andrew Kelley
ea6a076065 stage2: fix use-after-free in elf linker code 2020-08-25 13:36:15 -07:00
Andrew Kelley
84d50c892d stage2: astgen: kill the "lvalue" ResultLoc tag 2020-08-24 16:13:10 -07:00
Andrew Kelley
16d54c70eb stage2: getErrorValue takes advantage of HashMap getOrPut API 2020-08-24 15:41:59 -07:00
Vexu
5de9aac749 stage2: error set types 2020-08-24 15:36:42 -07:00
Vexu
bc1d55a1d1 stage2: fix field access of array pointers 2020-08-24 15:36:42 -07:00
Vexu
1520e084cb stage2: implement accessing error values 2020-08-24 15:36:42 -07:00
Vexu
e9b15ac9a0 stage2: error set declarations 2020-08-24 15:36:42 -07:00
Vexu
16d7db59ed stage2: anyframe and error union types 2020-08-24 15:36:42 -07:00
Vexu
d62c12e077 stage2: astgen prefix ops 2020-08-24 15:36:42 -07:00
Jakub Konka
43b6d0e4b1
Add (empty) __TEXT segment load command
Also, link against `libSystem` by default when targeting macOS.

Signed-off-by: Jakub Konka <kubkon@jakubkonka.com>
2020-08-24 21:18:27 +02:00
Jakub Konka
9745e7b512 Clean up draft for merging into upstream
Signed-off-by: Jakub Konka <kubkon@jakubkonka.com>
2020-08-24 17:59:44 +02:00
Jakub Konka
1698e6d7a7 Link against libSystem when generating Mach-O exe
This is required when generating an exe on macOS.

Signed-off-by: Jakub Konka <kubkon@jakubkonka.com>
2020-08-24 17:59:44 +02:00
Jakub Konka
2516db9645 Specify path to dyld in Mach-O
This is required since an exec on macOS always has to link against
libSystem.dylib.

Signed-off-by: Jakub Konka <kubkon@jakubkonka.com>
2020-08-24 17:59:44 +02:00
joachimschmidt557
4f2618e75b stage2: Add Hello World test for ARM backend 2020-08-23 23:13:41 +02:00
joachimschmidt557
b2254023e4 stage2: Implement setReg, call, ret, asm for ARM
These changes enable a Hello World example. However, all implemented
codegen is not yet feature-complete.

- asm only supports 'svc #0' at the moment
- call only supports leaf functions at the moment
- setReg uses a naive method at the moment
2020-08-23 22:33:47 +02:00
joachimschmidt557
1c53c07053 stage2: Implement genBreakpoint for ARM 2020-08-23 22:29:00 +02:00
joachimschmidt557
f31cee5393 Start working on stage2 ARM backend
- add codegen/arm.zig with some basic functionality (load/store,
  data processing, branching, software interrupts)
2020-08-23 22:27:46 +02:00
Andrew Kelley
54f3b0a560 stage2: clean up SPU Mk II code
* move SPU code from std to self hosted compiler
 * change std lib comments to be descriptive rather than prescriptive
 * avoid usingnamespace
 * fix case style of error codes
 * remove duplication of producer_string
 * generalize handling of less than 64 bit arch pointers
 * clean up SPU II related test harness code
2020-08-22 13:36:08 -07:00
Noam Preil
24efbf5ddf Codegen: Move REX assert to comptime 2020-08-22 12:45:29 -07:00
Noam Preil
ad9df43e49 Tests: limit SPU-II cycle count 2020-08-22 12:45:29 -07:00
Noam Preil
f448b518f8 SPU-II: use undefined1 as breakpoint 2020-08-22 12:45:29 -07:00
Noam Preil
222e23c678 Linker: make defaults read-only 2020-08-22 12:45:29 -07:00
Noam Preil
096c5d5e4b Tests: implement SPU-II harness 2020-08-22 12:45:29 -07:00
Noam Preil
fa1d18a155 Linker: fix GOT production on 16-bit targets 2020-08-22 12:45:29 -07:00
Noam Preil
3a9af0c88b SPU-II: Ignore @breakpoint for now 2020-08-22 12:45:29 -07:00
Noam Preil
f2fef240a1 SPU-II: Test harness skeleton 2020-08-22 12:45:29 -07:00
Noam Preil
f18636fa58 SPU-II: Add common definitions 2020-08-22 12:45:29 -07:00
Noam Preil
8c321f0cf5 SPU-II: Fix linking 2020-08-22 12:45:29 -07:00
Noam Preil
cdefc6acba SPU-II: Implement function calls 2020-08-22 12:45:29 -07:00
Noam Preil
d005ff16c6 SPU-II: undefined0 inline asm 2020-08-22 12:45:29 -07:00
Noam Preil
803a1025bb Targets: add SPU Mark II architecture 2020-08-22 12:45:29 -07:00
Andrew Kelley
29051a0674 stage2: codegen: fix crash
I forgot to do -Denable-qemu -Denable-wasmtime when testing yesterday,
sorry about that.

In reuseOperand, the code assumed a re-used register would be tracked in
the register table but that is not always the case.
2020-08-22 12:44:45 -07:00
Andrew Kelley
f18b92ef3a stage2: implement spilling registers to the stack 2020-08-21 23:36:21 -07:00
Andrew Kelley
89b6c47e04 stage2: decouple codegen.zig from ELF
See #6113 for an alternate way of doing this that we didn't end up
following.

Closes #6079.

I also took the opportunity here to extract C.zig and Elf.zig from
link.zig.
2020-08-21 13:25:59 -07:00
Andrew Kelley
e0a38f7f3e stage2: make the cache dir if it doesn't already exist 2020-08-20 23:53:34 -07:00
Andrew Kelley
f54b2e2da6 add missing mutability check in simplePtrType 2020-08-20 17:08:01 -07:00
Vexu
6a053ffcc8 stage2: comptime decl 2020-08-20 16:42:48 -07:00
Vexu
d312d64c9a stage2: slice types 2020-08-20 16:42:48 -07:00