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stage2: Implement setReg, call, ret, asm for ARM
These changes enable a Hello World example. However, all implemented codegen is not yet feature-complete. - asm only supports 'svc #0' at the moment - call only supports leaf functions at the moment - setReg uses a naive method at the moment
This commit is contained in:
joachimschmidt557
parent
1c53c07053
commit
b2254023e4
@ -1399,6 +1399,31 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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return self.fail(inst.base.src, "TODO implement calling runtime known function pointer", .{});
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}
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},
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.arm => {
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if (info.args.len > 0) return self.fail(inst.base.src, "TODO implement fn args for {}", .{self.target.cpu.arch});
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if (inst.func.cast(ir.Inst.Constant)) |func_inst| {
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if (func_inst.val.cast(Value.Payload.Function)) |func_val| {
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const func = func_val.func;
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const got = &elf_file.program_headers.items[elf_file.phdr_got_index.?];
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const ptr_bits = self.target.cpu.arch.ptrBitWidth();
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const ptr_bytes: u64 = @divExact(ptr_bits, 8);
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const got_addr = @intCast(u32, got.p_vaddr + func.owner_decl.link.elf.offset_table_index * ptr_bytes);
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// TODO only works with leaf functions
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// at the moment, which works fine for
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// Hello World, but not for real code
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// of course. Add pushing lr to stack
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// and popping after call
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try self.genSetReg(inst.base.src, .lr, .{ .memory = got_addr });
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.blx(.al, .lr).toU32());
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} else {
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return self.fail(inst.base.src, "TODO implement calling bitcasted functions", .{});
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}
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} else {
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return self.fail(inst.base.src, "TODO implement calling runtime known function pointer", .{});
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}
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},
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else => return self.fail(inst.base.src, "TODO implement call for {}", .{self.target.cpu.arch}),
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}
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} else if (self.bin_file.cast(link.File.MachO)) |macho_file| {
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@ -1455,6 +1480,9 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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.riscv64 => {
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.jalr(.zero, 0, .ra).toU32());
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},
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.arm => {
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.bx(.al, .lr).toU32());
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},
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else => return self.fail(src, "TODO implement return for {}", .{self.target.cpu.arch}),
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}
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return .unreach;
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@ -1705,6 +1733,36 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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return self.fail(inst.base.src, "TODO implement support for more SPU II assembly instructions", .{});
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}
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},
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.arm => {
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for (inst.inputs) |input, i| {
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if (input.len < 3 or input[0] != '{' or input[input.len - 1] != '}') {
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return self.fail(inst.base.src, "unrecognized asm input constraint: '{}'", .{input});
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}
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const reg_name = input[1 .. input.len - 1];
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const reg = parseRegName(reg_name) orelse
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return self.fail(inst.base.src, "unrecognized register: '{}'", .{reg_name});
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const arg = try self.resolveInst(inst.args[i]);
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try self.genSetReg(inst.base.src, reg, arg);
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}
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if (mem.eql(u8, inst.asm_source, "svc #0")) {
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.svc(.al, 0).toU32());
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} else {
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return self.fail(inst.base.src, "TODO implement support for more arm assembly instructions", .{});
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}
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if (inst.output) |output| {
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if (output.len < 4 or output[0] != '=' or output[1] != '{' or output[output.len - 1] != '}') {
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return self.fail(inst.base.src, "unrecognized asm output constraint: '{}'", .{output});
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}
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const reg_name = output[2 .. output.len - 1];
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const reg = parseRegName(reg_name) orelse
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return self.fail(inst.base.src, "unrecognized register: '{}'", .{reg_name});
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return MCValue{ .register = reg };
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} else {
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return MCValue.none;
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}
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},
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.riscv64 => {
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for (inst.inputs) |input, i| {
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if (input.len < 3 or input[0] != '{' or input[input.len - 1] != '}') {
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@ -1898,6 +1956,58 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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fn genSetReg(self: *Self, src: usize, reg: Register, mcv: MCValue) InnerError!void {
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switch (arch) {
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.arm => switch (mcv) {
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.dead => unreachable,
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.ptr_stack_offset => unreachable,
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.ptr_embedded_in_code => unreachable,
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.unreach, .none => return, // Nothing to do.
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.undef => {
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if (!self.wantSafety())
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return; // The already existing value will do just fine.
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// Write the debug undefined value.
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return self.genSetReg(src, reg, .{ .immediate = 0xaaaaaaaa });
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},
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.immediate => |x| {
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// TODO better analysis of x to determine the
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// least amount of necessary instructions (use
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// more intelligent rotating)
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if (x <= math.maxInt(u8)) {
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, 0, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
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return;
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} else if (x <= math.maxInt(u16)) {
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// TODO Use movw Note: Not supported on
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// all ARM targets!
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, 0, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, 0, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 8), 12)).toU32());
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} else if (x <= math.maxInt(u32)) {
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// TODO Use movw and movt Note: Not
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// supported on all ARM targets! Also TODO
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// write constant to code and load
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// relative to pc
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// immediate: 0xaabbccdd
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// mov reg, #0xaa
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// orr reg, reg, #0xbb, 24
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// orr reg, reg, #0xcc, 16
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// orr reg, reg, #0xdd, 8
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, 0, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, 0, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 8), 12)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, 0, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 16), 8)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, 0, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 24), 4)).toU32());
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return;
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} else {
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return self.fail(src, "ARM registers are 32-bit wide", .{});
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}
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},
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.memory => |addr| {
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// The value is in memory at a hard-coded address.
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// If the type is a pointer, it means the pointer address is at this memory location.
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try self.genSetReg(src, reg, .{ .immediate = addr });
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.ldr(.al, reg, reg, Instruction.Offset.none).toU32());
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},
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else => return self.fail(src, "TODO implement getSetReg for arm {}", .{mcv}),
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},
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.riscv64 => switch (mcv) {
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.dead => unreachable,
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.ptr_stack_offset => unreachable,
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@ -157,7 +157,7 @@ pub const Instruction = union(enum) {
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fixed_2: u22 = 0b0001_0010_1111_1111_1111_00,
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cond: u4,
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},
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SoftwareInterrupt: packed struct {
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SupervisorCall: packed struct {
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comment: u24,
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fixed: u4 = 0b1111,
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cond: u4,
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@ -344,7 +344,7 @@ pub const Instruction = union(enum) {
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.SingleDataTransfer => |v| @bitCast(u32, v),
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.Branch => |v| @bitCast(u32, v),
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.BranchExchange => |v| @bitCast(u32, v),
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.SoftwareInterrupt => |v| @bitCast(u32, v),
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.SupervisorCall => |v| @bitCast(u32, v),
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.Breakpoint => |v| @intCast(u32, v.imm4) | (@intCast(u32, v.fixed_1) << 4) | (@intCast(u32, v.imm12) << 8) | (@intCast(u32, v.fixed_2_and_cond) << 20),
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};
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}
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@ -355,8 +355,8 @@ pub const Instruction = union(enum) {
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cond: Condition,
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opcode: Opcode,
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s: u1,
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rn: Register,
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rd: Register,
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rn: Register,
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op2: Operand,
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) Instruction {
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return Instruction{
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@ -394,7 +394,7 @@ pub const Instruction = union(enum) {
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.b = byte_word,
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.u = up_down,
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.p = pre_post,
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.i = if (offset == .Immediate) 1 else 0,
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.i = if (offset == .Immediate) 0 else 1,
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},
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};
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}
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@ -419,9 +419,9 @@ pub const Instruction = union(enum) {
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};
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}
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fn softwareInterrupt(cond: Condition, comment: u24) Instruction {
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fn supervisorCall(cond: Condition, comment: u24) Instruction {
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return Instruction{
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.SoftwareInterrupt = .{
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.SupervisorCall = .{
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.cond = @enumToInt(cond),
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.comment = comment,
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},
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@ -536,10 +536,12 @@ pub const Instruction = union(enum) {
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return branchExchange(cond, rn, 1);
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}
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// Software interrupt
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// Supervisor Call
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pub fn swi(cond: Condition, comment: u24) Instruction {
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return softwareInterrupt(cond, comment);
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pub const swi = svc;
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pub fn svc(cond: Condition, comment: u24) Instruction {
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return supervisorCall(cond, comment);
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}
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// Breakpoint
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@ -562,7 +564,7 @@ test "serialize instructions" {
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},
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.{ // mov r4, r2
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.inst = Instruction.mov(.al, 0, .r4, Instruction.Operand.reg(.r2, Instruction.Operand.Shift.none)),
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.expected = 0b1110_00_0_1101_0_0100_0000_00000000_0010,
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.expected = 0b1110_00_0_1101_0_0000_0100_00000000_0010,
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},
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.{ // mov r0, #42
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.inst = Instruction.mov(.al, 0, .r0, Instruction.Operand.imm(42, 0)),
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@ -570,11 +572,11 @@ test "serialize instructions" {
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},
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.{ // ldr r0, [r2, #42]
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.inst = Instruction.ldr(.al, .r0, .r2, Instruction.Offset.imm(42)),
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.expected = 0b1110_01_1_1_1_0_0_1_0010_0000_000000101010,
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.expected = 0b1110_01_0_1_1_0_0_1_0010_0000_000000101010,
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},
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.{ // str r0, [r3]
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.inst = Instruction.str(.al, .r0, .r3, Instruction.Offset.none),
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.expected = 0b1110_01_1_1_1_0_0_0_0011_0000_000000000000,
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.expected = 0b1110_01_0_1_1_0_0_0_0011_0000_000000000000,
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},
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.{ // b #12
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.inst = Instruction.b(.al, 12),
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@ -588,8 +590,8 @@ test "serialize instructions" {
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.inst = Instruction.bx(.al, .lr),
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.expected = 0b1110_0001_0010_1111_1111_1111_0001_1110,
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},
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.{ // swi #0
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.inst = Instruction.swi(.al, 0),
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.{ // svc #0
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.inst = Instruction.svc(.al, 0),
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.expected = 0b1110_1111_0000_0000_0000_0000_0000_0000,
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},
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.{ // bkpt #42
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@ -756,6 +756,7 @@ pub const Type = extern union {
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.fn_ccc_void_no_args, // represents machine code; not a pointer
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.function, // represents machine code; not a pointer
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=> return switch (target.cpu.arch) {
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.arm => 4,
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.riscv64 => 2,
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else => 1,
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},
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