13065 Commits

Author SHA1 Message Date
Andrew Kelley
cec766f73c stage2: compile error for duplicate switch value on boolean 2021-03-31 18:30:23 -07:00
jacob gw
fedc9ebd26 stage2: cbe: restore all previously passing tests! 2021-03-31 18:09:45 -07:00
Andrew Kelley
3cebaaad1c astgen: improved handling of coercion
GenZir struct now has rl_ty_inst field which tracks the result location
type (if any) a block expects all of its results to be coerced to.

Remove a redundant coercion on const local initialization with a
specified type.

Switch expressions, during elision of store_to_block_ptr instructions,
now re-purpose them to be type coercion when the block has a type in the
result location.
2021-03-31 18:05:37 -07:00
Andrew Kelley
08eedc962d Sema: fix else case code generation for switch 2021-03-31 16:17:47 -07:00
Andrew Kelley
abd06d8eab stage2: clean up RangeSet and fix swapped Sema switch logic for lhs/rhs 2021-03-31 15:39:04 -07:00
Andrew Kelley
e272c29c16 Sema: implement switch validation for ranges 2021-03-31 15:06:03 -07:00
Andrew Kelley
c7b09be8de AstGen: improve switch expressions
* use the proper result location strategy even when there are noreturn
   prongs in the switch expression
 * when using break_operand strategy, actually omit the
   store_to_block_ptr instructions rather than eliding them.
 * for both strategies, properly handle noreturn prongs.
2021-03-31 12:37:20 -07:00
Andrew Kelley
549af582e7 AstGen: switch expressions properly handle result locations 2021-03-30 23:57:22 -07:00
Andrew Kelley
2a1dd174cd stage2: rework AstGen for switch expressions
The switch_br ZIR instructions are now switch_block instructions. This
avoids a pointless block always surrounding a switchbr in emitted ZIR
code.

Introduce typeof_elem ZIR instruction for getting the type of the
element of a pointer value in 1 instruction.

Change typeof to be un_node, not un_tok.

Introduce switch_capture ZIR instructions for obtaining the capture
value of switch prongs.

Introduce Sema.resolveBody for when you want to extract a *Inst out of a
block and you know that there is only going to be 1 break from it.

What's not working yet: AstGen does not correctly elide
store instructions when it turns out that the result location does not
need to be used as a pointer.

Also Sema validation code for duplicate switch items is not yet
implemented.
2021-03-30 21:28:36 -07:00
Andrew Kelley
195ddab2be Sema: implement switch expressions
The logic for putting ranges into the else prong is moved from AstGen to
Sema. However, logic to emit multi-items the same as single-items cannot
be done until TZIR supports mapping multiple items to the same block of
code. This will be simple to represent when we do the upcoming TZIR memory
layout changes.

Not yet implemented in this commit is the validation of duplicate
values. The trick is going to be emitting error messages with accurate
source locations, without adding extra source nodes to the ZIR
switch instruction.

This will be done by computing the respective AST node based on the
switch node (which we do have available), only when a compile error
occurs and we need to know the source location to attach the message to.
2021-03-29 21:59:08 -07:00
Andrew Kelley
623d5f442c stage2: guidance on how to implement switch expressions
Here's what I think the ZIR should be. AstGen is not yet implemented to
match this, and the main implementation of analyzeSwitch in Sema is not
yet implemented to match it either.

Here are some example byte size reductions from master branch, with the
ZIR memory layout from this commit:

```
switch (foo) {
  a => 1,
  b => 2,
  c => 3,
  d => 4,
}
```

184 bytes (master) => 40 bytes (this branch)

```
switch (foo) {
  a, b => 1,
  c..d, e, f => 2,
  g => 3,
  else => 4,
}
```

240 bytes (master) => 80 bytes (this branch)
2021-03-28 23:12:26 -07:00
Andrew Kelley
281a7baaea Merge remote-tracking branch 'origin/master' into zir-memory-layout
Wanted to make sure those new test cases still pass.

Also grab that CI fix so we can get those green check marks.
2021-03-28 19:42:43 -07:00
Andrew Kelley
8f469c1127 stage2: fix error sets 2021-03-28 19:40:21 -07:00
jacob gw
0005b34637 stage2: implement sema for @errorToInt and @intToError 2021-03-28 18:22:01 -07:00
Andrew Kelley
175adc0bd7 ci: update msys2 installer 2021-03-28 17:49:28 -07:00
Andrew Kelley
bb5cfbcb72
Merge pull request #8305 from jedisct1/base64
std/base64: cleanups & support url-safe and other non-padded variants
2021-03-28 17:11:07 -07:00
Isaac Freund
f80f8a7a78
AstGen: pass *GenZir as the first arg, not *Module
This avoids the unnecessary scope.getGenZir() virtual call for both
convenience and performance.
2021-03-28 22:42:17 +02:00
Isaac Freund
d5d88087dd
translate-c: fix typo made in prior commit 2021-03-28 22:29:37 +02:00
Isaac Freund
d123a5ec67
AstGen: scope result location related functions 2021-03-28 19:53:38 +02:00
Isaac Freund
402f87a213
stage2: rename WipZirCode => AstGen, astgen.zig => AstGen.zig 2021-03-28 19:10:10 +02:00
Jonathan Knezek
bbe6a0dddd Add a test & fix for std.fmt.fmtDuration 2021-03-28 15:44:15 +02:00
Frank Denis
6993087edc Remove the base64 unsafe decoder 2021-03-28 14:32:34 +02:00
Frank Denis
99bed37fc7 Add more variants 2021-03-28 14:32:34 +02:00
Frank Denis
b8c019ef49 std/base64: cleanups & support url-safe and other non-padded variants
This makes a few changes to the base64 codecs.

* The padding character is optional. The common "URL-safe" variant, in
particular, is generally not used with padding. This is also the case for
password hashes, so having this will avoid code duplication with bcrypt,
scrypt and other functions.
* The URL-safe variant is added. Instead of having individual constants
for each parameter of each variant, we are now grouping these in a
struct. So, `standard_pad_char` just becomes `standard.pad_char`.
* Types are not `snake_case`'d any more. So, `standard_encoder` becomes
`standard.Encoder`, as it is a type.
* Creating a decoder with ignored characters required the alphabet and
padding. Now, `standard.decoderWithIgnore(<ignored chars>)` returns a
decoder with the standard parameters and the set of ignored chars.
* Whatever applies to `standard.*` obviously also works with `url_safe.*`
* the `calcSize()` interface was inconsistent, taking a length in the
encoder, and a slice in the encoder. Rename the variant that takes a
slice to `calcSizeForSlice()`.
* In the decoder with ignored characters, add `calcSizeUpperBound()`,
which is more useful than the one that takes a slice in order to size
a fixed buffer before we have the data.
* Return `error.InvalidCharacter` when the input actually contains
characters that are neither padding nor part of the alphabet. If we
hit a padding issue (which includes extra bits at the end),
consistently return `error.InvalidPadding`.
* Don't keep the `char_in_alphabet` array permanently in a decoder;
it is only required for sanity checks during initialization.
* Tests are unchanged, but now cover both the standard (padded) and
the url-safe (non-padded) variants.
* Add an error set, rename `OutputTooSmallError` to `NoSpaceLeft`
to match the `hex2bin` equivalent.
2021-03-28 14:32:34 +02:00
Evan Haas
ab9324e604 translate-c: intcast compound assignment operand if different-sized integer
Use transCCast to cast the RHS of compound assignment if necessary.
2021-03-28 15:21:12 +03:00
lithdew
c8d721aa42 array_hash_map: decrement entries slice len after popping from entries in pop() to prevent oob 2021-03-28 11:02:37 +02:00
Jakub Konka
54b42a7596 azure: run pacman with -Sy 2021-03-28 11:01:57 +02:00
Andrew Kelley
68f4eb0f67 stage2: fully implement Type.eql for pointers
Also fixed abiAlignment - for pointers it was returning the abi
alignment inside the type, rather than of the pointer itself. There is
now `ptrAlignment` for getting the alignment inside the type of
pointers.
2021-03-27 23:55:19 -07:00
Andrew Kelley
95cc457d97 stage2: enable passing tests 2021-03-26 23:54:36 -07:00
Andrew Kelley
1f5617ac07 stage2: implement bitwise expr and error literals 2021-03-26 23:46:37 -07:00
Andrew Kelley
da731e18c9 stage2: implement source location: .node_offset_var_decl_ty 2021-03-26 18:35:15 -07:00
Andrew Kelley
a72bfd00cf astgen: fix continue expressions 2021-03-26 18:26:39 -07:00
Isaac Freund
a217ad59c7
astgen: fix result location for sliced objects 2021-03-26 23:39:29 +01:00
Isaac Freund
22338d7816
astgen: implement float literals 2021-03-26 15:46:50 +01:00
Isaac Freund
d8ee8794e1
astgen: implement more builtin functions 2021-03-26 15:20:11 +01:00
Isaac Freund
5eea13f5cc
astgen: implement slicing 2021-03-26 11:46:42 +01:00
Andrew Kelley
b2deaf8027 stage2: improve source locations of Decl access
* zir.Code: introduce a decls array. This is so that `decl_val` and
   `decl_ref` instructions can refer to a Decl with a u32 and therefore
   they can also store a source location. This is needed for proper
   compile error reporting.
 * astgen uses a hash map to avoid redundantly adding a Decl to the
   decls array.
 * fixed reporting "instruction illegal outside function body" instead
   of the desired message "unable to resolve comptime value".
 * astgen skips emitting dbg_stmt instructions in comptime scopes.
 * astgen has some logic to avoid adding unnecessary type coercion
   instructions for common values.
2021-03-25 23:45:17 -07:00
Andrew Kelley
4bfcd105ef stage2: fix @compileLog. 2021-03-25 20:11:23 -07:00
Andrew Kelley
4fd3a2e8e8 astgen: fix var decl source locations 2021-03-25 19:39:30 -07:00
Andrew Kelley
b9c5a1fdf5 astgen: fix for loop expressions
also rename the ZIR instruction `deref_node` to `load`.
2021-03-25 19:25:26 -07:00
Michael Dusan
9f01598a49 zig build: use ZIG_GLOBAL_CACHE_DIR
- move ZIG_GLOBAL_CACHE_DIR to `introspect`
- cleanup some dead fields from stage1 codegen
2021-03-25 22:05:21 -04:00
Jakub Konka
f1e324216d zld: parse archive's table of contents 2021-03-25 22:48:04 +01:00
Andrew Kelley
399bb2e154 astgen: fix array access 2021-03-25 13:03:54 -07:00
lithdew
4ce212739b os/linux: handle ECONNRESET for recv 2021-03-25 12:41:51 -07:00
Veikka Tuominen
df0f7f4692 translate-c: stop creating unnamed decls for typedefs child types 2021-03-25 16:59:26 +02:00
Sreehari S
5c28b8cd11 boot_services: implement locateDevicePath 2021-03-25 16:45:43 +02:00
Andrew Kelley
31023de6c4 stage2: implement inline while
Introduce "inline" variants of ZIR tags:
 * block => block_inline
 * repeat => repeat_inline
 * break => break_inline
 * condbr => condbr_inline

The inline variants perform control flow at compile-time, and they
utilize the return value of `Sema.analyzeBody`.

`analyzeBody` now returns an Index, not a Ref, which is the ZIR index of
a break instruction. This effectively communicates both the intended
break target block as well as the operand, allowing parent blocks to
find out whether they, in turn, should return the break instruction up the
call stack, or accept the operand as the block's result and continue
analyzing instructions in the block.

Additionally:
 * removed the deprecated ZIR tag `block_comptime`.
 * removed `break_void_node` so that all break instructions use the same Data.
 * zir.Code: remove the `root_start` and `root_len` fields. There is now
   implied to be a block at index 0 for the root body. This is so that
   `break_inline` has something to point at and we no longer need the
   special instruction `break_flat`.
 * implement source location byteOffset() for .node_offset_if_cond
   .node_offset_for_cond is probably redundant and can be deleted.

We don't have `comptime var` supported yet, so this commit adds a test
that at least makes sure the condition is required to be comptime known
for `inline while`.
2021-03-25 00:55:36 -07:00
Andrew Kelley
12d18a36e5 stage2: enable passing tests 2021-03-24 20:58:38 -07:00
Andrew Kelley
01bfd835bb stage2: clean up break / noreturn astgen
* Module.addBreak and addBreakVoid return zir.Inst.Index not Ref
   because Index is the simpler type and we never need a Ref for these.
 * astgen: make noreturn stuff return the unreachable_value and avoid
   unnecessary calls to rvalue()
 * breakExpr: avoid unnecessary access into the tokens array
 * breakExpr: fix incorrect `@intCast` (previously this unsafely
   casted an Index to a Ref)
2021-03-24 20:45:14 -07:00
Timon Kruiper
ea42ab34ab stage2: add block test cases llvm backend 2021-03-24 19:54:03 -07:00