43 Commits

Author SHA1 Message Date
Felix Queißner
7c74edec8d
Adds new cpu architectures propeller1 and propeller2. (#21563)
* Adds new cpu architectures propeller1 and propeller2.

These cpu architectures allow targeting the Parallax Propeller 1 and Propeller 2, which are both very special microcontrollers with 512 registers and 8 cpu cores.

Resolves #21559

* Adds std.elf.EM.PROPELLER and std.elf.EM.PROPELLER2
* Fixes missing switch prongs in src/codegen/llvm.zig
* Fixes order in std.Target.Arch

---------

Co-authored-by: Felix "xq" Queißner <git@random-projects.net>
2024-10-04 13:53:28 -07:00
Andrew Kelley
4f8d244e7e remove formatted panics
implements #17969
2024-09-26 12:35:14 -07:00
Alex Rønne Petersen
d1901c744c std.Target: Remove Cpu.Arch.dxil and ObjectFormat.dxcontainer.
See: https://devblogs.microsoft.com/directx/directx-adopting-spir-v

Since we never hooked up the (experimental) DirectX LLVM backend, we've never
actually supported targeting DXIL in Zig. With Microsoft moving away from DXIL,
that seems very unlikely to change.
2024-09-23 17:17:25 -07:00
mlugg
4650e5b9fc
Sema: clean up cmpNumeric
There is one minor language change here, which is that comparisons of
the form `comptime_inf < runtime_f32` have their results comptime-known.
This is consistent with comparisons against comptime NaN for instance,
which are always comptime known. A corresponding behavior test is added.

This fixes a bug with int comparison elision which my previous commit
somehow triggered. `Sema.compareIntsOnlyPossibleResult` is much cleaner
now!
2024-09-17 11:00:38 +01:00
mlugg
0fe3fd01dd
std: update std.builtin.Type fields to follow naming conventions
The compiler actually doesn't need any functional changes for this: Sema
does reification based on the tag indices of `std.builtin.Type` already!
So, no zig1.wasm update is necessary.

This change is necessary to disallow name clashes between fields and
decls on a type, which is a prerequisite of #9938.
2024-08-28 08:39:59 +01:00
David Rubin
61e8a6c008
remove some stale code
- Don't create an `inner_sema` in `unionFields`
- Remove assertions of the sema owner, when we literally just set it
2024-08-26 12:27:34 -07:00
David Rubin
f777b29832
fix up merge conflicts with master 2024-08-25 22:43:57 -07:00
David Rubin
ce92ccccc9
sema: resolve{Struct,Union}Inner don't throw away Semas
before this, calls to `resolveTypeFieldsStruct` (now renamed to the more correct `resolveStructFieldTypes`) would just throw away the sema that `resolveStructInner` created and create its own. There is no reason to do this, and we fix it to preserve the sema through it all.
2024-08-25 15:18:20 -07:00
David Rubin
1c1feba08e
remove mod aliases for Zcus 2024-08-25 15:17:40 -07:00
David Rubin
80cd53d3bb
sema: clean-up {union,struct}FieldAlignment and friends
My main gripes with this design were that it was incorrectly namespaced, the naming was inconsistent and a bit wrong (`fooAlign` vs `fooAlignment`).

This commit moves all the logic from `PerThread.zig` to use the zcu + tid system that the previous couple commits introduce.
I've organized and merged the functions to be a bit more specific to their own purpose.

- `fieldAlignment` takes a struct or union type, an index, and a Zcu (or the Sema version which takes a Pt), and gives you the alignment of the field at the index.
- `structFieldAlignment` takes the field type itself, and provides the logic to handle special cases, such as externs.

A design goal I had in mind was to avoid using the word 'struct' in the function name, when it worked for things that aren't structs, such as unions.
2024-08-25 15:16:46 -07:00
David Rubin
b4bb64ce78
sema: rework type resolution to use Zcu when possible 2024-08-25 15:16:42 -07:00
Jacob Young
4a132d4bce Type: fix inconsistency between zig fmt and @typeName 2024-08-22 20:08:04 -04:00
mlugg
de49a9a173
Zir: add instructions to fetch std.builtin types
This replaces the constant `Zir.Inst.Ref` tags (and the analagous tags
in `Air.Inst.Ref`, `InternPool.Index`) referring to types in
`std.builtin` with a ZIR instruction `extended(builtin_type(...))` which
instructs Sema to fetch such a type, effectively as if it were a
shorthand for the ZIR for `@import("std").builtin.xyz`.

Previously, this was achieved through constant tags in `Ref`. The
analagous `InternPool` indices began as `simple_type` values, and were
later rewritten to the correct type information. This system was kind of
brittle, and more importantly, isn't compatible with incremental
compilation of std, since incremental compilation relies on the ability
to recreate types at different indices when they change. Replacing the
old system with this instruction slightly increases the size of ZIR, but
it simplifies logic and allows incremental compilation to work correctly
on the standard library.

This shouldn't have a significant impact on ZIR size or compiler
performance, but I will take measurements in the PR to confirm this.
2024-08-18 18:10:59 +01:00
mlugg
895267c916 frontend: incremental progress
This commit makes more progress towards incremental compilation, fixing
some crashes in the frontend. Notably, it fixes the regressions introduced
by #20964. It also cleans up the "outdated file root" mechanism, by
virtue of deleting it: we now detect outdated file roots just after
updating ZIR refs, and re-scan their namespaces.
2024-08-17 18:50:10 -04:00
Jacob Young
ef11bc9899 Dwarf: rework self-hosted debug info from scratch
This is in preparation for incremental and actually being able to debug
executables built by the x86_64 backend.
2024-08-16 15:22:55 -04:00
Linus Groh
4ef956ef14 std.Target: Rename c_type_* functions to camel case
From https://ziglang.org/documentation/master/#Names:

> If `x` is otherwise callable, then `x` should be `camelCase`.
2024-08-12 00:36:51 +01:00
mlugg
153e7d6235
frontend: give all container types namespaces
Eliding the namespace when a container type has no decls was an
experiment in saving memory, but it ended up causing more trouble than
it was worth in various places. So, take the small memory hit for
reified types, and just give every container type a namespace.
2024-08-11 07:30:21 +01:00
mlugg
548a087faf
compiler: split Decl into Nav and Cau
The type `Zcu.Decl` in the compiler is problematic: over time it has
gained many responsibilities. Every source declaration, container type,
generic instantiation, and `@extern` has a `Decl`. The functions of
these `Decl`s are in some cases entirely disjoint.

After careful analysis, I determined that the two main responsibilities
of `Decl` are as follows:
* A `Decl` acts as the "subject" of semantic analysis at comptime. A
  single unit of analysis is either a runtime function body, or a
  `Decl`. It registers incremental dependencies, tracks analysis errors,
  etc.
* A `Decl` acts as a "global variable": a pointer to it is consistent,
  and it may be lowered to a specific symbol by the codegen backend.

This commit eliminates `Decl` and introduces new types to model these
responsibilities: `Cau` (Comptime Analysis Unit) and `Nav` (Named
Addressable Value).

Every source declaration, and every container type requiring resolution
(so *not* including `opaque`), has a `Cau`. For a source declaration,
this `Cau` performs the resolution of its value. (When #131 is
implemented, it is unsolved whether type and value resolution will share
a `Cau` or have two distinct `Cau`s.) For a type, this `Cau` is the
context in which type resolution occurs.

Every non-`comptime` source declaration, every generic instantiation,
and every distinct `extern` has a `Nav`. These are sent to codegen/link:
the backends by definition do not care about `Cau`s.

This commit has some minor technically-breaking changes surrounding
`usingnamespace`. I don't think they'll impact anyone, since the changes
are fixes around semantics which were previously inconsistent (the
behavior changed depending on hashmap iteration order!).

Aside from that, this changeset has no significant user-facing changes.
Instead, it is an internal refactor which makes it easier to correctly
model the responsibilities of different objects, particularly regarding
incremental compilation. The performance impact should be negligible,
but I will take measurements before merging this work into `master`.

Co-authored-by: Jacob Young <jacobly0@users.noreply.github.com>
Co-authored-by: Jakub Konka <kubkon@jakubkonka.com>
2024-08-11 07:29:41 +01:00
Ryan Liptak
304519da27 Make Type.intAbiAlignment match LLVM alignment for x86-windows target
During the LLVM 18 upgrade, two changes were made that changed `@alignOf(u64)` to 4 for the x86-windows target:

- `Type.maxIntAlignment` was made to return 16 for x86 (200e06b). Before that commit, `maxIntAlignment` was 8 for windows/uefi and 4 for everything else
- `Type.intAbiAlignment` was made to return 4 for 33...64 (7e1cba7 + e89d6fc). Before those commits, `intAbiAlignment` would return 8, since the maxIntAlignment for x86-windows was 8 (and for other targets, the `maxIntAlignment` of 4 would clamp the `intAbiAlignment` to 4)

`src/codegen/llvm.zig` has its own alignment calculations that no longer match the values returned from the `Type` functions. For the x86-windows target, this loop:

ddcb7b1c11/src/codegen/llvm.zig (L558-L567)

when the `size` is 64 will set `abi` and `pref` to 64 (meaning an align of 8 bytes), which doesn't match the `Type` alignment of 4.

This commit makes `Type.intAbiAlignment` match the alignment calculated in `codegen/llvm.zig`.

Fixes #20047
Fixes #20466
Fixes #20469
2024-08-07 00:59:46 -07:00
Alex Rønne Petersen
c8ca05e93a
std.Target: Remove sparcel architecture tag.
What is `sparcel`, you might ask? Good question!

If you take a peek in the SPARC v8 manual, §2.2, it is quite explicit that SPARC
v8 is a big-endian architecture. No little-endian or mixed-endian support to be
found here.

On the other hand, the SPARC v9 manual, in §3.2.1.2, states that it has support
for mixed-endian operation, with big-endian mode being the default.

Ok, so `sparcel` must just be referring to SPARC v9 running in little-endian
mode, surely?

Nope:

* 40b4fd7a3e/llvm/lib/Target/Sparc/SparcTargetMachine.cpp (L226)
* 40b4fd7a3e/llvm/lib/Target/Sparc/SparcTargetMachine.cpp (L104)

So, `sparcel` in LLVM is referring to some sort of fantastical little-endian
SPARC v8 architecture. I've scoured the internet and I can find absolutely no
evidence that such a thing exists or has ever existed. In fact, I can find no
evidence that a little-endian implementation of SPARC v9 ever existed, either.
Or any SPARC version, actually!

The support was added here: https://reviews.llvm.org/D8741

Notably, there is no mention whatsoever of what CPU this might be referring to,
and no justification given for the "but some are little" comment added in the
patch.

My best guess is that this might have been some private exercise in creating a
little-endian version of SPARC that never saw the light of day. Given that SPARC
v8 explicitly doesn't support little-endian operation (let alone little-endian
instruction encoding!), and no CPU is known to be implemented as such, I think
it's very reasonable for us to just remove this support.
2024-07-30 06:30:25 +02:00
Alex Rønne Petersen
1e9278d718
std.Target: Remove spir/spir64 architecture tags.
These were for very old OpenCL have been long abandoned in favor of SPIR-V.

* https://github.com/KhronosGroup/SPIR
* https://github.com/KhronosGroup/SPIR-Tools
2024-07-30 06:30:25 +02:00
Alex Rønne Petersen
d1d95294fd std.Target.Cpu.Arch: Remove the aarch64_32 tag.
This is a misfeature that we inherited from LLVM:

* https://reviews.llvm.org/D61259
* https://reviews.llvm.org/D61939

(`aarch64_32` and `arm64_32` are equivalent.)

I truly have no idea why this triple passed review in LLVM. It is, to date, the
*only* tag in the architecture component that is not, in fact, an architecture.
In reality, it is just an ILP32 ABI for AArch64 (*not* AArch32).

The triples that use `aarch64_32` look like `aarch64_32-apple-watchos`. Yes,
that triple is exactly what you think; it has no ABI component. They really,
seriously did this.

Since only Apple could come up with silliness like this, it should come as no
surprise that no one else uses `aarch64_32`. Later on, a GNU ILP32 ABI for
AArch64 was developed, and support was added to LLVM:

* https://reviews.llvm.org/D94143
* https://reviews.llvm.org/D104931

Here, sanity seems to have prevailed, and a triple using this ABI looks like
`aarch64-linux-gnu_ilp32` as you would expect.

As can be seen from the diffs in this commit, there was plenty of confusion
throughout the Zig codebase about what exactly `aarch64_32` was. So let's just
remove it. In its place, we'll use `aarch64-watchos-ilp32`,
`aarch64-linux-gnuilp32`, and so on. We'll then translate these appropriately
when talking to LLVM. Hence, this commit adds the `ilp32` ABI tag (we already
have `gnuilp32`).
2024-07-28 19:44:52 -07:00
Alex Rønne Petersen
db8bc4770c
std.Target: Remove the tce/tcele arch tags.
There is no obvious reason why this would be relevant for Zig to target. I
rather question the value of LLVM even having target triple code for this, too.

See: https://blog.llvm.org/2010/06/tce-project-co-design-of-application.html
See: https://github.com/cpc/llvmtce
2024-07-21 22:38:30 +02:00
Alex Rønne Petersen
21cc5a2044
std.Target: Remove the shave arch tag.
This was added as an architecture to LLVM's target triple parser and the Clang
driver in 2015. No backend ever materialized as far as I can see (same for GCC).
In 2016, other code referring to it started using "Myriad" instead. Ultimately,
all code related to it that isn't in the target triple parser was removed. It
seems to be a real product, just... literally no one seems to know anything
about the ISA. I figure after almost a decade with no public ISA documentation
to speak of, and no LLVM backend to reference, it's probably safe to assume that
we're not going to learn much about this ISA, making it useless for Zig.

See: 1b5767f72b
See: 84a7564b28
See: 8cfe9d8f2a
2024-07-21 22:38:30 +02:00
Alex Rønne Petersen
f1e0c35db4
std.Target: Remove hsail/hsail64 arch tags.
This seems to just be dead.

See: https://github.com/search?q=repo%3Allvm%2Fllvm-project%20hsail&type=code
See: https://github.com/HSAFoundation/HSAIL-Tools/commits/master
2024-07-21 22:38:30 +02:00
Alex Rønne Petersen
67a052df81
std.Target: Remove amdil/amdil64 arch tags.
This is really obscure and no one is 100% sure what it is. It seems to be old
and unused. My suspicion is that it's just an old term for "AMDGPU" before it
was upstreamed to LLVM.

See: https://github.com/search?q=repo%3Allvm%2Fllvm-project+amdil&type=code
2024-07-21 22:38:30 +02:00
Alex Rønne Petersen
c825b567b2
std.Target: Remove the r600 arch tag.
These are quite old GPUs, and it is unlikely that Zig will ever be able to
target them.

See: https://en.wikipedia.org/wiki/Radeon_HD_2000_series
2024-07-21 22:38:30 +02:00
Alex Rønne Petersen
9848623e62
std.Target: Remove the renderscript32/renderscript64 arch tags.
It's dead: https://developer.android.com/guide/topics/renderscript/migrate
2024-07-21 22:38:30 +02:00
Alex Rønne Petersen
af8205e25e
std.Target: Remove nacl OS specifier and le32/le64 arch specifiers.
Native Client is dead.

https://developer.chrome.com/docs/native-client
2024-07-20 05:08:16 +02:00
mlugg
f84a4953d2
Value: eliminate static recursion loop from value printing 2024-07-16 11:38:21 +01:00
mlugg
67cd14dbdb
Type: avoid incorrect type resolution calls 2024-07-16 11:38:20 +01:00
mlugg
b1d3d48f68
Type,Value: mark ResolveStrat parameter of type queries as comptime
This eliminates the statically-reachable recursion loop between code
generation backends and Sema. This is beneficial for optimizers
(although I do not measure any performance improvement for this change),
and for profilers.
2024-07-16 11:38:20 +01:00
Jacob Young
a1053e8e1d InternPool: add and use a mutate mutex for each list
This allows the mutate mutex to only be locked during actual grows,
which are rare. For the lists that didn't previously have a mutex, this
change has little effect since grows are rare and there is zero
contention on a mutex that is only ever locked by one thread.  This
change allows `extra` to be mutated without racing with a grow.
2024-07-13 04:47:38 -04:00
Jacob Young
8f292431b0 InternPool: fix undefined decl fully qualified name
This is now possible after moving `File.Index` to `*File` mapping into
intern pool.
2024-07-10 11:20:08 -04:00
Jacob Young
3d2dfbe828 InternPool: add FileIndex to *File mapping 2024-07-10 11:20:08 -04:00
Jacob Young
667b4f9054 Zcu: cache fully qualified name on Decl
This avoids needing to mutate the intern pool from backends.
2024-07-10 11:10:49 -04:00
Jacob Young
bdae01ab04 InternPool: implement and use thread-safe list for extra and limbs 2024-07-07 22:59:52 -04:00
Jacob Young
92ddb959a7 InternPool: implement and use thread-safe list for items 2024-07-07 22:59:52 -04:00
Jacob Young
525f341f33 Zcu: introduce PerThread and pass to all the functions 2024-07-07 22:59:52 -04:00
Andrew Kelley
74346b0f79 frontend: TrackedInst stores FileIndex instead of path digest
The purpose of using path digest was to reference a file in a
serializable manner. Now that there is a stable index associated with
files, it is a superior way to accomplish that goal, since removes one
layer of indirection, and makes TrackedInst 8 bytes instead of 20.

The saved Zig Compiler State file for "hello world" goes from 1.3M to
1.2M with this change.
2024-07-04 17:56:01 -07:00
Andrew Kelley
30ec43a6c7 Zcu: extract permanent state from File
Primarily, this commit removes 2 fields from File, relying on the data
being stored in the `files` field, with the key as the path digest, and
the value as the struct decl corresponding to the File. This table is
serialized into the compiler state that survives between incremental
updates.

Meanwhile, the File struct remains ephemeral data that can be
reconstructed the first time it is needed by the compiler process, as
well as operated on by independent worker threads.

A key outcome of this commit is that there is now a stable index that
can be used to refer to a File. This will be needed when serializing
error messages to survive incremental compilation updates.
2024-07-04 17:51:35 -07:00
mlugg
0e5335aaf5
compiler: rework type resolution, fully resolve all types
I'm so sorry.

This commit was just meant to be making all types fully resolve by
queueing resolution at the moment of their creation. Unfortunately, a
lot of dominoes ended up falling. Here's what happened:

* I added a work queue job to fully resolve a type.
* I realised that from here we could eliminate `Sema.types_to_resolve`
  if we made function codegen a separate job. This is desirable for
  simplicity of both spec and implementation.
* This led to a new AIR traversal to detect whether any required type is
  unresolved. If a type in the AIR failed to resolve, then we can't run
  codegen.
* Because full type resolution now occurs by the work queue job, a bug
  was exposed whereby error messages for type resolution were associated
  with the wrong `Decl`, resulting in duplicate error messages when the
  type was also resolved "by" its owner `Decl` (which really *all*
  resolution should be done on).
* A correct fix for this requires using a different `Sema` when
  performing type resolution: we need a `Sema` owned by the type. Also
  note that this fix is necessary for incremental compilation.
* This means a whole bunch of functions no longer need to take `Sema`s.
  * First-order effects: `resolveTypeFields`, `resolveTypeLayout`, etc
  * Second-order effects: `Type.abiAlignmentAdvanced`, `Value.orderAgainstZeroAdvanced`, etc

The end result of this is, in short, a more correct compiler and a
simpler language specification. This regressed a few error notes in the
test cases, but nothing that seems worth blocking this change.

Oh, also, I ripped out the old code in `test/src/Cases.zig` which
introduced a dependency on `Compilation`. This dependency was
problematic at best, and this code has been unused for a while. When we
re-enable incremental test cases, we must rewrite their executor to use
the compiler server protocol.
2024-07-04 21:01:42 +01:00
mlugg
2f0f1efa6f
compiler: type.zig -> Type.zig 2024-07-04 21:01:42 +01:00