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std.Target: Remove the shave arch tag.

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This was added as an architecture to LLVM's target triple parser and the Clang
driver in 2015. No backend ever materialized as far as I can see (same for GCC).
In 2016, other code referring to it started using "Myriad" instead. Ultimately,
all code related to it that isn't in the target triple parser was removed. It
seems to be a real product, just... literally no one seems to know anything
about the ISA. I figure after almost a decade with no public ISA documentation
to speak of, and no LLVM backend to reference, it's probably safe to assume that
we're not going to learn much about this ISA, making it useless for Zig.

See: 1b5767f72b
See: 84a7564b28
See: 8cfe9d8f2a
This commit is contained in:
Alex Rønne Petersen 2024-07-21 14:13:37 +02:00
parent f1e0c35db4
commit 21cc5a2044
No known key found for this signature in database
6 changed files with 0 additions and 17 deletions
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3
lib/compiler/aro/aro/target.zig vendored
View File

@ -482,7 +482,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
.nvptx,
.spir,
.kalimba,
.shave,
.lanai,
.wasm32,
.aarch64_32,
@ -522,7 +521,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
.lanai,
.m68k,
.msp430,
.shave,
.sparcel,
.spu_2,
.tce,
@ -628,7 +626,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
.spirv32 => "spirv32",
.spirv64 => "spirv64",
.kalimba => "kalimba",
.shave => "shave",
.lanai => "lanai",
.wasm32 => "wasm32",
.wasm64 => "wasm64",

8
lib/std/Target.zig
View File

@ -1017,7 +1017,6 @@ pub const Cpu = struct {
spirv32,
spirv64,
kalimba,
shave,
lanai,
wasm32,
wasm64,
@ -1154,7 +1153,6 @@ pub const Cpu = struct {
.nvptx => .NONE,
.spir => .NONE,
.kalimba => .CSR_KALIMBA,
.shave => .NONE,
.lanai => .LANAI,
.wasm32 => .NONE,
.aarch64_32 => .AARCH64,
@ -1211,7 +1209,6 @@ pub const Cpu = struct {
.nvptx => .Unknown,
.spir => .Unknown,
.kalimba => .Unknown,
.shave => .Unknown,
.lanai => .Unknown,
.wasm32 => .Unknown,
.aarch64_32 => .ARM64,
@ -1273,7 +1270,6 @@ pub const Cpu = struct {
.thumb,
.spir,
.spir64,
.shave,
.ve,
.spu_2,
// GPU bitness is opaque. For now, assume little endian.
@ -1759,7 +1755,6 @@ pub const DynamicLinker = struct {
.spir,
.spir64,
.kalimba,
.shave,
.lanai,
.ve,
.dxil,
@ -1860,7 +1855,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
.nvptx,
.spir,
.kalimba,
.shave,
.lanai,
.wasm32,
.aarch64_32,
@ -2381,7 +2375,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
.spir,
.spirv32,
.kalimba,
.shave,
.ve,
.spu_2,
.xtensa,
@ -2493,7 +2486,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
.spir,
.spirv32,
.kalimba,
.shave,
.ve,
.spu_2,
.xtensa,

1
src/Type.zig
View File

@ -1654,7 +1654,6 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {
.kalimba,
.spirv,
.spirv32,
.shave,
.spir64,
.ve,
.spirv64,

1
src/Zcu.zig
View File

@ -3258,7 +3258,6 @@ pub fn atomicPtrAlignment(
.spir,
.kalimba,
.lanai,
.shave,
.wasm32,
.csky,
.spirv32,

3
src/codegen/llvm.zig
View File

@ -88,7 +88,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
.spirv32 => "spirv32",
.spirv64 => "spirv64",
.kalimba => "kalimba",
.shave => "shave",
.lanai => "lanai",
.wasm32 => "wasm32",
.wasm64 => "wasm64",
@ -305,7 +304,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
.spirv32 => .spirv32,
.spirv64 => .spirv64,
.kalimba => .kalimba,
.shave => .shave,
.lanai => .lanai,
.wasm32 => .wasm32,
.wasm64 => .wasm64,
@ -12080,7 +12078,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
// LLVM backends that have no initialization functions.
.tce,
.tcele,
.shave,
.spir,
.spir64,
.spirv,

1
src/target.zig
View File

@ -158,7 +158,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
.spirv32,
.spirv64,
.kalimba,
.shave,
.lanai,
.wasm32,
.wasm64,