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std.Target: Remove the renderscript32/renderscript64 arch tags.

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It's dead: https://developer.android.com/guide/topics/renderscript/migrate
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Alex Rønne Petersen 2024-07-21 14:02:24 +02:00
parent 08cddaf11c
commit 9848623e62
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6 changed files with 0 additions and 34 deletions
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6
lib/compiler/aro/aro/target.zig vendored
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@ -488,7 +488,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
.shave,
.lanai,
.wasm32,
.renderscript32,
.aarch64_32,
.spirv32,
.loongarch32,
@ -504,7 +503,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
.hsail64 => copy.cpu.arch = .hsail,
.spir64 => copy.cpu.arch = .spir,
.spirv64 => copy.cpu.arch = .spirv32,
.renderscript64 => copy.cpu.arch = .renderscript32,
.loongarch64 => copy.cpu.arch = .loongarch32,
.mips64 => copy.cpu.arch = .mips,
.mips64el => copy.cpu.arch = .mipsel,
@ -550,7 +548,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
.hsail64,
.spir64,
.spirv64,
.renderscript64,
.loongarch64,
.mips64,
.mips64el,
@ -574,7 +571,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
.nvptx => copy.cpu.arch = .nvptx64,
.powerpc => copy.cpu.arch = .powerpc64,
.powerpcle => copy.cpu.arch = .powerpc64le,
.renderscript32 => copy.cpu.arch = .renderscript64,
.riscv32 => copy.cpu.arch = .riscv64,
.sparc => copy.cpu.arch = .sparc64,
.spir => copy.cpu.arch = .spir64,
@ -651,8 +647,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
.lanai => "lanai",
.wasm32 => "wasm32",
.wasm64 => "wasm64",
.renderscript32 => "renderscript32",
.renderscript64 => "renderscript64",
.ve => "ve",
// Note: spu_2 is not supported in LLVM; this is the Zig arch name
.spu_2 => "spu_2",

16
lib/std/Target.zig
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@ -1026,8 +1026,6 @@ pub const Cpu = struct {
lanai,
wasm32,
wasm64,
renderscript32,
renderscript64,
ve,
spu_2,
@ -1167,7 +1165,6 @@ pub const Cpu = struct {
.shave => .NONE,
.lanai => .LANAI,
.wasm32 => .NONE,
.renderscript32 => .NONE,
.aarch64_32 => .AARCH64,
.aarch64 => .AARCH64,
.aarch64_be => .AARCH64,
@ -1182,7 +1179,6 @@ pub const Cpu = struct {
.hsail64 => .NONE,
.spir64 => .NONE,
.wasm64 => .NONE,
.renderscript64 => .NONE,
.amdgcn => .AMDGPU,
.bpfel => .BPF,
.bpfeb => .BPF,
@ -1231,7 +1227,6 @@ pub const Cpu = struct {
.shave => .Unknown,
.lanai => .Unknown,
.wasm32 => .Unknown,
.renderscript32 => .Unknown,
.aarch64_32 => .ARM64,
.aarch64 => .ARM64,
.aarch64_be => .ARM64,
@ -1246,7 +1241,6 @@ pub const Cpu = struct {
.hsail64 => .Unknown,
.spir64 => .Unknown,
.wasm64 => .Unknown,
.renderscript64 => .Unknown,
.amdgcn => .Unknown,
.bpfel => .Unknown,
.bpfeb => .Unknown,
@ -1299,8 +1293,6 @@ pub const Cpu = struct {
.thumb,
.spir,
.spir64,
.renderscript32,
.renderscript64,
.shave,
.ve,
.spu_2,
@ -1794,8 +1786,6 @@ pub const DynamicLinker = struct {
.kalimba,
.shave,
.lanai,
.renderscript32,
.renderscript64,
.ve,
.dxil,
.loongarch32,
@ -1901,7 +1891,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
.shave,
.lanai,
.wasm32,
.renderscript32,
.aarch64_32,
.spirv32,
.loongarch32,
@ -1922,7 +1911,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
.hsail64,
.spir64,
.wasm64,
.renderscript64,
.amdgcn,
.bpfel,
.bpfeb,
@ -2426,7 +2414,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
.spirv32,
.kalimba,
.shave,
.renderscript32,
.ve,
.spu_2,
.xtensa,
@ -2453,7 +2440,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
.s390x,
.spir64,
.spirv64,
.renderscript64,
=> 8,
.aarch64,
@ -2545,7 +2531,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
.spirv32,
.kalimba,
.shave,
.renderscript32,
.ve,
.spu_2,
.xtensa,
@ -2579,7 +2564,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
.s390x,
.spir64,
.spirv64,
.renderscript64,
=> 8,
.aarch64,

2
src/Type.zig
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@ -1655,14 +1655,12 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {
.hsail,
.spir,
.kalimba,
.renderscript32,
.spirv,
.spirv32,
.shave,
.amdil64,
.hsail64,
.spir64,
.renderscript64,
.ve,
.spirv64,
.dxil,

2
src/Zcu.zig
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@ -3263,7 +3263,6 @@ pub fn atomicPtrAlignment(
.lanai,
.shave,
.wasm32,
.renderscript32,
.csky,
.spirv32,
.dxil,
@ -3286,7 +3285,6 @@ pub fn atomicPtrAlignment(
.hsail64,
.spir64,
.wasm64,
.renderscript64,
.ve,
.spirv64,
.loongarch64,

6
src/codegen/llvm.zig
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@ -97,8 +97,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
.lanai => "lanai",
.wasm32 => "wasm32",
.wasm64 => "wasm64",
.renderscript32 => "renderscript32",
.renderscript64 => "renderscript64",
.ve => "ve",
.spu_2 => return error.@"LLVM backend does not support SPU Mark II",
};
@ -321,8 +319,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
.lanai => .lanai,
.wasm32 => .wasm32,
.wasm64 => .wasm64,
.renderscript32 => .renderscript32,
.renderscript64 => .renderscript64,
.ve => .ve,
.spu_2 => .UnknownArch,
};
@ -12106,8 +12102,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
.spirv32,
.spirv64,
.kalimba,
.renderscript32,
.renderscript64,
.dxil,
=> {},

2
src/target.zig
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@ -167,8 +167,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
.lanai,
.wasm32,
.wasm64,
.renderscript32,
.renderscript64,
.ve,
=> true,