171 Commits

Author SHA1 Message Date
Andrew Kelley
913393fd3b stage2: first pass over Module.zig for AIR memory layout 2021-07-20 12:19:16 -07:00
Andrew Kelley
ee6432537e stage2: first pass over codegen.zig for AIR memory layout 2021-07-20 12:19:16 -07:00
Andrew Kelley
3c3abaf390 stage2: update liveness analysis to new AIR memory layout
It's pretty compact, with each AIR instruction only taking up 4 bits,
plus a sparse table for special instructions such as conditional branch,
switch branch, and function calls with more than 2 arguments.
2021-07-20 12:18:14 -07:00
Andrew Kelley
5d6f7b44c1 stage2: rework AIR memory layout
This commit changes the AIR file and the documentation of the memory
layout. The actual work of modifying the surrounding code (in Sema and
codegen) is not yet done.
2021-07-20 12:18:14 -07:00
Jacob G-W
968d1ecf17 stage2 plan9: add aarch64 support 2021-07-11 01:58:26 -04:00
Andrew Kelley
476faef97a plan9 cleanups
* rename files to adhere to conventions
 * remove unnecessary function / optionality
 * fix merge conflict
 * better panic message
 * remove unnecessary TODO comment
 * proper namespacing of declarations
 * clean up documentation comments
 * no copyright header needed for a brand new zig file that is not
   copied from anywhere
2021-07-08 14:24:16 -07:00
Jacob G-W
4eb778fc3e plan9 linker: remove unused stuff 2021-07-08 14:12:08 -07:00
Jacob G-W
1c2facaf6b stage2: include enough inline asm support for more plan9 syscalls
Also make the exit more correct by exiting 0 rather than random
stuff on the stack.
2021-07-08 14:12:08 -07:00
Jacob G-W
db2d5b49c6 plan9 linker: use a global offset table
this simplifies stuff and makes us not have to use relocations
2021-07-08 14:12:07 -07:00
Jacob G-W
3e59c15025 plan9 linker: do relocations 2021-07-08 14:10:49 -07:00
Jacob G-W
798162e509 plan9 linker: make runnable binaries
We can now run binaries! (they segfault, but still run!)
2021-07-08 14:10:49 -07:00
Andrew Kelley
5c8bd443d9 stage2: fix if expressions on error unions
AstGen had the then-else logic backwards for if expressions
on error unions. This commit fixes it.

Turns out AstGen only really needs `is_non_null` and `is_non_err`,
and does not need the `is_null` or `is_err` variants. So I removed the
`is_null{,_ptr}` and `is_err{,_ptr}` ZIR instructions (-4) and
added `is_non_err`, `is_non_err_ptr` ZIR instructions (+2) for
a total of (-2) ZIR instructions, giving us a tiny bit more headroom
within the 256 tag limit. This required swapping the order of
then/else blocks in a handful of cases, but ultimately means the
ZIR will be in the same as source order, which is convenient
when debugging.

AIR code on the other hand, gains the `is_non_err` and `is_non_err_ptr`
instructions.

Sema: fix logic in zirErrUnionCode and zirErrUnionCodePtr returning the
wrong result type.
2021-07-07 19:50:56 -07:00
Andrew Kelley
5816997ae7 stage2: get tests passing
* implement enough of ret_err_value to pass wasm tests
 * only do the proper `@panic` implementation for the backends which
   support it, which is currently only the C backend. The other backends
   will see `@breakpoint(); unreachable;` same as before.
   - I plan to do AIR memory layout reworking as a prerequisite to
     fixing other backends, because that will help me put all the
     constants up front, which will allow the codegen to lower to memory
     without jumps.
 * `@panic` is implemented using anon decls for the message. Makes it
   easier on the backends. Might want to look into re-using decls for
   this in the future.
 * implement DWARF .debug_info for pointer-like optionals.
2021-07-07 14:17:04 -07:00
Andrew Kelley
06412e04f9 cleanups related to unused params 2021-06-21 17:03:04 -07:00
Jacob G-W
9fffffb07b fix code broken from previous commit 2021-06-21 17:03:03 -07:00
Jacob G-W
641ecc260f std, src, doc, test: remove unused variables 2021-06-21 17:03:03 -07:00
g-w1
e13a182990
stage2 Sema: implement @intToPtr (#9144)
Co-authored-by: Veikka Tuominen <git@vexu.eu>
2021-06-21 18:47:34 +03:00
Jacob G-W
a95fdb0635 stage2: simplify codegen for errorToInt and intToError
We can just use bitcast instead of error_to_int, int_to_error since
errorToInt and intToError do not actually do anything, just change types.
This allows us to remove 2 air ops that were the exact same as bitcast
2021-06-21 18:45:28 +03:00
joachimschmidt557
96c60bcca5 stage2 codegen: Remove hacks for discontinued SPU II backend 2021-06-09 21:37:23 +03:00
Martin Wickham
fc9430f567 Breaking hash map changes for 0.8.0
- hash/eql functions moved into a Context object
- *Context functions pass an explicit context
- *Adapted functions pass specialized keys and contexts
- new getPtr() function returns a pointer to value
- remove functions renamed to fetchRemove
- new remove functions return bool
- removeAssertDiscard deleted, use assert(remove(...)) instead
- Keys and values are stored in separate arrays
- Entry is now {*K, *V}, the new KV is {K, V}
- BufSet/BufMap functions renamed to match other set/map types
- fixed iterating-while-modifying bug in src/link/C.zig
2021-06-03 17:02:16 -05:00
joachimschmidt557
e8236551ab stage2: Move BlockData out of ir.Inst.Block 2021-05-22 21:15:25 -04:00
Andrew Kelley
79dee75b1c stage2: rename ir.zig to air.zig
We've settled on the nomenclature for the artifacts the compiler
pipeline produces:

1. Tokens
2. AST (Abstract Syntax Tree)
3. ZIR (Zig Intermediate Representation)
4. AIR (Analyzed Intermediate Representation)
5. Machine Code

Renaming `ir` identifiers to `air` will come with the inevitable
air-memory-layout branch that I plan to start after the 0.8.0 release.
2021-05-22 14:29:16 -07:00
Andrew Kelley
615d45da77 Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgen
Conflicts:
 * src/codegen/spirv.zig
 * src/link/SpirV.zig

We're going to want to improve the stage2 test harness to print
the source file name when a compile error occurs otherwise std lib
contributors are going to see some confusing CI failures when they cause
stage2 AstGen compile errors.
2021-05-17 19:30:38 -07:00
joachimschmidt557
65cee0b3fd stage2 ARM: correct spilling in genArmMul as well 2021-05-17 17:18:01 -04:00
Andrew Kelley
597082adf4 Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgen
Conflicts:
 * build.zig
 * src/Compilation.zig
 * src/codegen/spirv/spec.zig
 * src/link/SpirV.zig
 * test/stage2/darwin.zig
   - this one might be problematic; start.zig looks for `main` in the
     root source file, not `_main`. Not sure why there is an underscore
     there in master branch.
2021-05-15 21:44:38 -07:00
Andrew Kelley
07606d12da stage2: remove SPU Mark II backend
As it stands, the backend is incomplete, and there is no active contributor,
making it dead weight.

However, anyone is free to resurrect this backend at any time.
2021-05-15 21:25:42 -07:00
Andrew Kelley
dc036f5b6f codegen: implement const value rendering for ints <= 64 bits 2021-05-15 21:00:15 -07:00
joachimschmidt557
8b4e91e18c stage2 register manager: clean up API and add more unit tests 2021-05-14 15:12:33 -04:00
Andrew Kelley
c9cc09a3bf Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgen
Conflicts:
 * lib/std/os/linux.zig
 * lib/std/os/windows/bits.zig
 * src/Module.zig
 * src/Sema.zig
 * test/stage2/test.zig

Mainly I wanted Jakub's new macOS code for respecting stack size, since
we now depend on it for debug builds able to pass one of the test cases
for recursive comptime function calls with `@setEvalBranchQuota`.

The conflicts were all trivial.
2021-05-12 16:41:20 -07:00
joachimschmidt557
d211dc37c8 stage2 ARM: Overhaul of genArmBinOp 2021-05-09 08:48:58 +02:00
Andrew Kelley
b88d381dec
Merge pull request #8474 from gracefuu/grace/encode-instruction
stage2 x86_64: encoding helpers, fix bugs
2021-05-09 01:36:51 -04:00
Andrew Kelley
eadcefc124 stage2: dbg_stmt ZIR instructions have line/col
instead of node indexes.

 * AstGen: dbg_stmt instructions now have line and column indexes,
   relative to the parent declaration. This allows codegen to emit debug
   info without having the source bytes, tokens, or AST nodes loaded
   in memory.
 * ZIR: each decl has the absolute line number. This allows computing
   line numbers from offsets without consulting source code bytes.

Memory management: creating a function definition does not prematurely
set the Decl arena. Instead the function is allocated with the general
purpose allocator.

Codegen no longer looks at source code bytes for any reason. They can
remain unloaded from disk.
2021-05-01 21:57:52 -07:00
Andrew Kelley
0c71d2fdc1 stage2: implement semantic analysis for functions and global vars
* AstGen: add missing `break_inline` for comptime blocks.
 * Module: call getTree() in byteOffset(). This generates the AST when
   using cached ZIR and compile errors need to be reported.
 * Scope.File: distinguish between successful ZIR generation and AIR
   generation (when Decls in scope have been scanned).
   - `semaFile` correctly avoids doing work twice.
 * Implement first pass at `lookupInNamespace`. It has various TODOs
   left, such as `usingnamespace`, and setting up Decl dependencies.
2021-04-28 22:43:26 -07:00
Andrew Kelley
f86469bc5e stage2: semaDecl properly analyzes the decl block
Also flattened out Decl TypedValue fields into
ty, val, has_tv
and add relevant fields to Decl for alignment and link section.
2021-04-28 16:57:01 -07:00
Andrew Kelley
df24ce52b1 Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgen
In particular I wanted to take advantage of the new hex float parsing
code.
2021-04-28 14:57:38 -07:00
joachimschmidt557
3a55cda14d stage2 register manager: Use an array instead of a hashmap for tracking
allocated registers
2021-04-25 13:20:53 -04:00
Andrew Kelley
e86cee258c Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgen
In particular I wanted the change that makes `suspend;` illegal in the
parser.
2021-04-24 10:44:41 -07:00
jacob gw
6b944492b5 stage2: fix compile error in codegen 2021-04-20 17:08:05 -04:00
Andrew Kelley
4630e3891c AstGen: implement inline asm output 2021-04-19 18:44:59 -07:00
joachimschmidt557
fbda9991f4 stage2 codegen: Fix silent bug in reuseOperand 2021-04-17 20:57:26 -04:00
gracefu
cfeb412a42
stage2 x86_64: fix incorrect comment in genX8664BinMath
Co-authored-by: joachimschmidt557 <joachim.schmidt557@outlook.com>
2021-04-16 15:21:17 +08:00
gracefu
dc13662725
stage2 x86_64: force 64 bit mode when loading address of GOT
Co-authored-by: joachimschmidt557 <joachim.schmidt557@outlook.com>
2021-04-16 15:21:17 +08:00
gracefu
1e63e8d8b6
stage2 x86_64: fix codegen ensureCapacity bug for function calls
Co-authored-by: joachimschmidt557 <joachim.schmidt557@outlook.com>
2021-04-16 15:21:17 +08:00
gracefu
62e755623f
stage2 x86_64: bugfix abi_size == 64 should be abi_size == 8 2021-04-16 15:21:17 +08:00
gracefu
b004c3da15
stage2 x86_64: try to fix RIP-relative offset to GOT for macho 2021-04-16 15:21:17 +08:00
gracefu
0409f9e024
stage2 x86_64: simplify inst encoder to a set of dumb helper fns 2021-04-16 15:21:17 +08:00
gracefu
c4b83ea021
stage2 x86_64: implement integer mul
This was also an experiment to see if it were easier to implement a new
feature when using the instruction encoder.

Verdict: It's not that much easier, but I think it's certainly much more
readable, because the description of the Instruction annotates what each
field means. Right now, precise knowledge of x86_64 instructions is
still required because things like when to set the 64-bit flag, how to
read x86_64 instruction references, etc. are still not automatically
done for you.

In the future, this interface might make it sligtly easier to write an
assembler for x86_64, by abstracting the bit-fiddling aspects of
instruction encoding.
2021-04-16 15:21:17 +08:00
gracefu
5bd464e386
stage2 x86_64: use abi size to determine 64-bit operation
From my very cursory reading, it seems that the register manager doesn't
distinguish between registers that are physically the same but have
different sizes.

In that case, this means that during codegen, we can't rely on
`reg.size()` when determining the width of the operations we have to
perform. Instead, we must use some form of `ty.abiSize(self.target.*)`
to determine the size of the type we're operating with. If this size is
64 bits, then we should enable 64-bit operation.

This fixed a bug in the codegen for spilling instructions, which was
overwriting the previous stack entry with zeroes. See the modified test
case in this commit.
2021-04-16 15:21:17 +08:00
gracefu
36df1526da
stage2 x86_64: refactor codegen to use inst encoder
There are parts of it that I didn't modify because the byte
representation was important (e.g. we need to know what the exact
byte position where we store the address into the offset table is)
2021-04-16 15:21:17 +08:00
Andrew Kelley
f458192e56 stage2: entry point via std lib and proper updated file detection
Instead of Module setting up the root_scope with the root source file,
instead, Module relies on the package table graph being set up properly,
and inside `update()`, it does the equivalent of `_ = @import("std");`.
This, in term, imports start.zig, which has the logic to call main (or
not). `Module` no longer has `root_scope` - the root source file is no
longer special, it's just in the package table mapped to "root".

I also went ahead and implemented proper detection of updated files.
mtime, inode, size, and source hash are kept in `Scope.File`.
During an update, iterate over `import_table` and stat each file to find
out which ones are updated.

The source hash is redundant with the source hash used by the struct
decl that corresponds to the file, so it should be removed in a future
commit before merging the branch.

 * AstGen: add "previously declared here" notes for variables shadowing
   decls.
 * Parse imports as structs. Module now calls `AstGen.structDeclInner`,
   which is called by `AstGen.containerDecl`.
   - `importFile` is a bit kludgy with how it handles the top level Decl
     that kinda gets merged into the struct decl at the end of the
     function. Be on the look out for bugs related to that as well as
     possibly cleaner ways to implement this.
 * Module: factor out lookupDeclName into lookupIdentifier and lookupNa
 * Rename `Scope.Container` to `Scope.Namespace`.
 * Delete some dead code.

This branch won't work until `usingnamespace` is implemented because it
relies on `@import("builtin").OutputMode` and `OutputMode` comes from a
`usingnamespace`.
2021-04-15 19:06:39 -07:00