This way I am hopeful they can be reused for every MIR lowering
function which follows a given encoding. Currently, support MI,
RM and MR encodings without SIB scaling.
Instead of a separate function, `coerceNum` for handling comptime-known
number coercion, outside of the main switch, the `coerce` function now
has a single big switch statement that decides the control flow based on
the zig type tag.
* Extract common logic between `zirStructInitEmpty` and
`zirStructInit`.
* `resolveTypeFields` additionally sets status to `have_layout` if the
total number of fields is 0.
Allocate a new program header and a new section to accomodate the read-only data
section ".rodata".
Separate TextBlock into multiple TextBlockList, to separate decl in different
sections.
If a Decl is not a function, it is added to the .rodata section.
While this is technically incorrect, proper handling of anyopaque, as well
as regular opaque, is probably best left until pointers to zero-sized types
having no bits is abolished.
The self-hosted compiler cannot yet deal with the print function that this
field enables. It is not critical, however, and allows us to remove formatting
from the list of neccesary features to implement to get the page allocator
working.
This caused zirParam instructions of parent blocks to be present in
inline analyzed blocks, and so function prototypes declared in the
inline blocks would also gain and add to the parameters in the
parent block.
Only block and block_inline are affected in this commit, as prototypes
and declarations are always generated in block_inline. This might need
to be resolved in a more general way at some point.
Previously, function parameter instructions for function prototypes would be
generated in the parent block. This caused issues in blocks where multiple
prototypes would be generated in, such as the block for struct fields for
example. This change introduces an inline block around every prototype such
that all parameters for a prototype are confined to a unique block.
This allows the inferred error set of comptime and inline invocations to be
resolved separately from the inferred error set of the runtime version or other
comptime/inline invocations.
* turns out MOV and other arithmetic instructions such as ADD can
naturally share the same lowering codepath (for the same variants)
* there are variants that are specific to ADD, or MOV which will be
implemented as standalone MIR tags
* tweak Isel tests to generate corresponding test cases for all
arithmetic instructions in comptime
* variant `0b11` when both `reg1 != .none` and `reg2 != .none` is
identical to `0b00` therefore it can safely be removed
* fix proper destination register size calculation when setting register from
another source register
* introduce `EmitResult` wrapper struct for easier manipulation of
intermediate emit results - this is mainly to track errors such as
size mismatch between operands
* create an informative `ErrorMsg` directly at the callsite
* ensure that every callsite of basic MOV MIR instruction follows the
Intel syntax (dst <- src)
* add extensive unit tests for MOV MIR -> Isel lowering
* leave TODOs for cases that are currently not handled and/or missing
* fix any ABI size mismatch between operands
Make `@returnAddress()` return for the BPF target, as the BPF target for
the time being does not support probing for the return address. Stack
traces for the general purpose allocator for the BPF target is also set
to not be captured.
