mirror of
https://github.com/ziglang/zig.git
synced 2026-02-20 08:14:48 +00:00
stage2: fix MOV MIR -> Isel lowering logic
* ensure that every callsite of basic MOV MIR instruction follows the Intel syntax (dst <- src) * add extensive unit tests for MOV MIR -> Isel lowering * leave TODOs for cases that are currently not handled and/or missing * fix any ABI size mismatch between operands
This commit is contained in:
Jakub Konka
parent
ef0566df78
commit
70bff2f4d5
@ -275,7 +275,9 @@ pub fn generate(
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.stack_align = undefined,
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.end_di_line = module_fn.rbrace_line,
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.end_di_column = module_fn.rbrace_column,
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.mir_to_air_map = if (builtin.mode == .Debug) std.AutoHashMap(Mir.Inst.Index, Air.Inst.Index).init(bin_file.allocator) else {},
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.mir_to_air_map = if (builtin.mode == .Debug)
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std.AutoHashMap(Mir.Inst.Index, Air.Inst.Index).init(bin_file.allocator)
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else {},
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};
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defer function.stack.deinit(bin_file.allocator);
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defer function.blocks.deinit(bin_file.allocator);
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@ -386,8 +388,8 @@ fn gen(self: *Self) InnerError!void {
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_ = try self.addInst(.{
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.tag = .mov,
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.ops = (Mir.Ops{
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.reg1 = .rsp,
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.reg2 = .rbp,
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.reg1 = .rbp,
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.reg2 = .rsp,
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}).encode(),
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.data = undefined,
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});
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@ -2838,8 +2840,8 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
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_ = try self.addInst(.{
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.tag = .mov,
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.ops = (Mir.Ops{
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.reg1 = registerAlias(reg, @intCast(u32, abi_size)),
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.reg2 = registerAlias(.rbp, @intCast(u32, abi_size)),
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.reg1 = .rbp,
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.reg2 = registerAlias(reg, @intCast(u32, abi_size)),
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.flags = 0b10,
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}).encode(),
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.data = .{ .imm = -@intCast(i32, adj_off) },
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@ -2925,7 +2927,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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_ = try self.addInst(.{
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.tag = .mov,
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.ops = (Mir.Ops{
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.reg1 = reg,
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.reg1 = registerAlias(reg, 4),
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}).encode(),
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.data = .{ .imm = @intCast(i32, x) },
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});
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@ -3055,15 +3057,14 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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if (off < std.math.minInt(i32) or off > std.math.maxInt(i32)) {
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return self.fail("stack offset too large", .{});
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}
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const ioff = -@intCast(i32, off);
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_ = try self.addInst(.{
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.tag = .mov,
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.ops = (Mir.Ops{
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.reg1 = registerAlias(reg, @intCast(u32, abi_size)),
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.reg2 = registerAlias(.rbp, @intCast(u32, abi_size)),
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.reg2 = .rbp,
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.flags = 0b01,
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}).encode(),
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.data = .{ .imm = ioff },
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.data = .{ .imm = -@intCast(i32, off) },
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});
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},
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}
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@ -11,8 +11,10 @@ const link = @import("../../link.zig");
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const log = std.log.scoped(.codegen);
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const math = std.math;
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const mem = std.mem;
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const testing = std.testing;
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const Air = @import("../../Air.zig");
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const Allocator = mem.Allocator;
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const DebugInfoOutput = @import("../../codegen.zig").DebugInfoOutput;
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const DW = std.dwarf;
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const Encoder = bits.Encoder;
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@ -46,6 +48,11 @@ const InnerError = error{
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EmitFail,
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};
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const EmitError = error{
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OutOfMemory,
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OperandSizeMismatch,
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};
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const Reloc = struct {
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/// Offset of the instruction.
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source: u64,
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@ -100,10 +107,7 @@ pub fn emitMir(emit: *Emit) InnerError!void {
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.sbb_scale_imm => try emit.mirArithScaleImm(.sbb, inst),
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.cmp_scale_imm => try emit.mirArithScaleImm(.cmp, inst),
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// Even though MOV is technically not an arithmetic op,
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// its structure can be represented using the same set of
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// opcode primitives.
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.mov => try emit.mirArith(.mov, inst),
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.mov => try emit.mirMov(inst),
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.mov_scale_src => try emit.mirArithScaleSrc(.mov, inst),
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.mov_scale_dst => try emit.mirArithScaleDst(.mov, inst),
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.mov_scale_imm => try emit.mirArithScaleImm(.mov, inst),
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@ -566,7 +570,6 @@ inline fn getArithOpCode(tag: Mir.Inst.Tag, enc: EncType) OpCode {
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.@"or" => .{ .opc = 0x81, .modrm_ext = 0x1 },
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.sbb => .{ .opc = 0x81, .modrm_ext = 0x3 },
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.cmp => .{ .opc = 0x81, .modrm_ext = 0x7 },
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.mov => .{ .opc = 0xc7, .modrm_ext = 0x0 },
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else => unreachable,
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},
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.mr => {
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@ -579,7 +582,6 @@ inline fn getArithOpCode(tag: Mir.Inst.Tag, enc: EncType) OpCode {
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.@"or" => 0x09,
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.sbb => 0x19,
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.cmp => 0x39,
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.mov => 0x89,
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else => unreachable,
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};
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return .{ .opc = opc, .modrm_ext = undefined };
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@ -594,7 +596,6 @@ inline fn getArithOpCode(tag: Mir.Inst.Tag, enc: EncType) OpCode {
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.@"or" => 0x0b,
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.sbb => 0x1b,
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.cmp => 0x3b,
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.mov => 0x8b,
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else => unreachable,
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};
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return .{ .opc = opc, .modrm_ext = undefined };
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@ -723,7 +724,7 @@ fn mirArith(emit: *Emit, tag: Mir.Inst.Tag, inst: Mir.Inst.Index) InnerError!voi
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// OP [reg1 + imm32], imm32
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// OP r/m64, imm32
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const payload = emit.mir.instructions.items(.data)[inst].payload;
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const imm_pair = emit.mir.extraData(Mir.ImmPair, payload).data;
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const imm_pair = Mir.extraData(emit.mir.extra, Mir.ImmPair, payload).data;
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const opcode = getArithOpCode(tag, .mi);
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const opc = if (ops.reg1.size() == 8) opcode.opc - 1 else opcode.opc;
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const encoder = try Encoder.init(emit.code, 11);
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@ -835,7 +836,7 @@ fn mirArithScaleImm(emit: *Emit, tag: Mir.Inst.Tag, inst: Mir.Inst.Index) InnerE
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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const scale = ops.flags;
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const payload = emit.mir.instructions.items(.data)[inst].payload;
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const imm_pair = emit.mir.extraData(Mir.ImmPair, payload).data;
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const imm_pair = Mir.extraData(emit.mir.extra, Mir.ImmPair, payload).data;
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const opcode = getArithOpCode(tag, .mi);
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const opc = if (ops.reg1.size() == 8) opcode.opc - 1 else opcode.opc;
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const encoder = try Encoder.init(emit.code, 2);
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@ -856,6 +857,240 @@ fn mirArithScaleImm(emit: *Emit, tag: Mir.Inst.Tag, inst: Mir.Inst.Index) InnerE
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encoder.imm32(imm_pair.operand);
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}
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fn mirMov(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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return mirMovImpl(
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emit.mir.instructions,
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emit.mir.extra,
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inst,
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emit.code,
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) catch |err| switch (err) {
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// TODO better formating of operands in case of an error
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error.OperandSizeMismatch => emit.fail("operand size mismatch", .{}),
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else => emit.fail("emit failed with error: {}", .{err}),
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};
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}
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fn mirMovImpl(
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mir_instructions: std.MultiArrayList(Mir.Inst).Slice,
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mir_extra: []const u32,
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inst: Mir.Inst.Index,
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code: *std.ArrayList(u8),
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) EmitError!void {
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const ops = Mir.Ops.decode(mir_instructions.items(.ops)[inst]);
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switch (ops.flags) {
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0b00 => blk: {
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if (ops.reg2 == .none) {
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// mov reg1, imm32
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// MI
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const imm = mir_instructions.items(.data)[inst].imm;
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const opc: u8 = if (ops.reg1.size() == 8) 0xc6 else 0xc7;
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const modrm_ext: u3 = 0x0;
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const encoder = try Encoder.init(code, 7);
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if (ops.reg1.size() == 16) {
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// 0x66 prefix switches to the non-default size; here we assume a switch from
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// the default 32bits to 16bits operand-size.
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// More info: https://www.cs.uni-potsdam.de/desn/lehre/ss15/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf#page=32&zoom=auto,-159,773
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encoder.opcode_1byte(0x66);
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}
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encoder.rex(.{
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.w = ops.reg1.size() == 64,
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.b = ops.reg1.isExtended(),
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});
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encoder.opcode_1byte(opc);
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encoder.modRm_direct(modrm_ext, ops.reg1.lowId());
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switch (ops.reg1.size()) {
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8 => {
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const imm8 = math.cast(i8, imm) catch return error.OperandSizeMismatch;
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encoder.imm8(imm8);
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},
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16 => {
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const imm16 = math.cast(i16, imm) catch return error.OperandSizeMismatch;
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encoder.imm16(imm16);
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},
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32, 64 => {
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encoder.imm32(imm);
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},
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else => unreachable,
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}
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break :blk;
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}
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// mov reg1, reg2
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// MR
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if (ops.reg1.size() != ops.reg2.size()) {
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return error.OperandSizeMismatch;
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}
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const opc: u8 = if (ops.reg1.size() == 8) 0x88 else 0x89;
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const encoder = try Encoder.init(code, 3);
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encoder.rex(.{
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.w = ops.reg1.size() == 64 and ops.reg2.size() == 64,
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.r = ops.reg2.isExtended(),
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.b = ops.reg1.isExtended(),
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});
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encoder.opcode_1byte(opc);
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encoder.modRm_direct(ops.reg2.lowId(), ops.reg1.lowId());
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},
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0b01 => blk: {
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const imm = mir_instructions.items(.data)[inst].imm;
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const opc: u8 = if (ops.reg1.size() == 8) 0x8a else 0x8b;
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if (ops.reg2 == .none) {
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// mov reg1, [imm32]
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// RM
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const encoder = try Encoder.init(code, 9);
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if (ops.reg1.size() == 16) {
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encoder.opcode_1byte(0x66);
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}
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encoder.rex(.{
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.w = ops.reg1.size() == 64,
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.r = ops.reg1.isExtended(),
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});
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encoder.opcode_1byte(opc);
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encoder.modRm_SIBDisp0(ops.reg1.lowId());
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encoder.sib_disp32();
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encoder.disp32(imm);
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break :blk;
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}
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// mov reg1, [reg2 + imm32]
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// RM
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// TODO handle 32-bit base register - requires prefix 0x67
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// Intel Manual, Vol 1, chapter 3.6 and 3.6.1
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if (ops.reg2.size() != 64) {
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return error.OperandSizeMismatch;
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}
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const encoder = try Encoder.init(code, 8);
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if (ops.reg1.size() == 16) {
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encoder.opcode_1byte(0x66);
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}
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encoder.rex(.{
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.w = ops.reg1.size() == 64,
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.r = ops.reg1.isExtended(),
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.b = ops.reg2.isExtended(),
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});
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encoder.opcode_1byte(opc);
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if (immOpSize(imm) == 8) {
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encoder.modRm_indirectDisp8(ops.reg1.lowId(), ops.reg2.lowId());
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encoder.disp8(@intCast(i8, imm));
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} else {
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encoder.modRm_indirectDisp32(ops.reg1.lowId(), ops.reg2.lowId());
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encoder.disp32(imm);
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}
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},
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0b10 => blk: {
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// TODO handle 32-bit base register - requires prefix 0x67
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// Intel Manual, Vol 1, chapter 3.6 and 3.6.1
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if (ops.reg1.size() != 64) {
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return error.OperandSizeMismatch;
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}
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if (ops.reg2 == .none) {
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// mov [reg1 + 0], imm32
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// MI
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// Base register reg1 can either be 64bit or 32bit in size.
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// TODO for memory operand, immediate operand pair, we currently
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// have no way of flagging whether the immediate can be 8-, 16- or
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// 32-bit and whether the corresponding memory operand is respectively
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// a byte, word or dword ptr.
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// TODO we currently don't have a way to flag imm32 64bit sign extended
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const imm = mir_instructions.items(.data)[inst].imm;
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const opc: u8 = 0xc7;
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const modrm_ext: u3 = 0x0;
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const encoder = try Encoder.init(code, 7);
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encoder.rex(.{
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.w = false,
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.b = ops.reg1.isExtended(),
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});
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encoder.opcode_1byte(opc);
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encoder.modRm_indirectDisp0(modrm_ext, ops.reg1.lowId());
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encoder.imm32(imm);
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break :blk;
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}
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// mov [reg1 + imm32], reg2
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// MR
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// We use size of source register reg2 to work out which
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// variant of memory ptr to pick:
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// * reg2 is 64bit - qword ptr
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// * reg2 is 32bit - dword ptr
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// * reg2 is 16bit - word ptr
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// * reg2 is 8bit - byte ptr
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const imm = mir_instructions.items(.data)[inst].imm;
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const opc: u8 = if (ops.reg2.size() == 8) 0x88 else 0x89;
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const encoder = try Encoder.init(code, 5);
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if (ops.reg2.size() == 16) {
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encoder.opcode_1byte(0x66);
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}
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encoder.rex(.{
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.w = ops.reg2.size() == 64,
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.r = ops.reg2.isExtended(),
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.b = ops.reg1.isExtended(),
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});
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encoder.opcode_1byte(opc);
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if (immOpSize(imm) == 8) {
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encoder.modRm_indirectDisp8(ops.reg2.lowId(), ops.reg1.lowId());
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encoder.disp8(@intCast(i8, imm));
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} else {
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encoder.modRm_indirectDisp32(ops.reg2.lowId(), ops.reg1.lowId());
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encoder.disp32(imm);
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}
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},
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0b11 => blk: {
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if (ops.reg2 == .none) {
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// mov [reg1 + imm32], imm32
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// MI
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// Base register reg1 can either be 64bit or 32bit in size.
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// TODO for memory operand, immediate operand pair, we currently
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// have no way of flagging whether the immediate can be 8-, 16- or
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// 32-bit and whether the corresponding memory operand is respectively
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// a byte, word or dword ptr.
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// TODO we currently don't have a way to flag imm32 64bit sign extended
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if (ops.reg1.size() != 64) {
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return error.OperandSizeMismatch;
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}
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const payload = mir_instructions.items(.data)[inst].payload;
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const imm_pair = Mir.extraData(mir_extra, Mir.ImmPair, payload).data;
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const imm_op = imm_pair.operand;
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const opc: u8 = 0xc7;
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const modrm_ext: u3 = 0x0;
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const encoder = try Encoder.init(code, 10);
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encoder.rex(.{
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.w = false,
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.b = ops.reg1.isExtended(),
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});
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encoder.opcode_1byte(opc);
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if (immOpSize(imm_pair.dest_off) == 8) {
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encoder.modRm_indirectDisp8(modrm_ext, ops.reg1.lowId());
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encoder.disp8(@intCast(i8, imm_pair.dest_off));
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} else {
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encoder.modRm_indirectDisp32(modrm_ext, ops.reg1.lowId());
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encoder.disp32(imm_pair.dest_off);
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}
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encoder.imm32(imm_op);
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break :blk;
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}
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// mov reg1, reg2
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// RM
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const opc: u8 = if (ops.reg1.size() == 8) 0x8a else 0x8b;
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const encoder = try Encoder.init(code, 3);
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encoder.rex(.{
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.w = ops.reg1.size() == 64 and ops.reg2.size() == 64,
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.r = ops.reg1.isExtended(),
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.b = ops.reg2.isExtended(),
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});
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encoder.opcode_1byte(opc);
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encoder.modRm_direct(ops.reg1.lowId(), ops.reg2.lowId());
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},
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}
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}
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fn immOpSize(imm: i32) u8 {
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blk: {
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_ = math.cast(i8, imm) catch break :blk;
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return 8;
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}
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blk: {
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_ = math.cast(i16, imm) catch break :blk;
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return 16;
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}
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return 32;
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}
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fn mirMovabs(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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const tag = emit.mir.instructions.items(.tag)[inst];
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assert(tag == .movabs);
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@ -897,7 +1132,7 @@ fn mirMovabs(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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if (is_64) {
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const payload = emit.mir.instructions.items(.data)[inst].payload;
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const imm64 = emit.mir.extraData(Mir.Imm64, payload).data;
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const imm64 = Mir.extraData(emit.mir.extra, Mir.Imm64, payload).data;
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encoder.imm64(imm64.decode());
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} else {
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const imm = emit.mir.instructions.items(.data)[inst].imm;
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@ -1003,7 +1238,7 @@ fn mirLeaRip(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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const end_offset = emit.code.items.len;
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if (@truncate(u1, ops.flags) == 0b0) {
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const payload = emit.mir.instructions.items(.data)[inst].payload;
|
||||
const imm = emit.mir.extraData(Mir.Imm64, payload).data.decode();
|
||||
const imm = Mir.extraData(emit.mir.extra, Mir.Imm64, payload).data.decode();
|
||||
encoder.disp32(@intCast(i32, @intCast(i64, imm) - @intCast(i64, end_offset - start_offset + 4)));
|
||||
} else {
|
||||
const got_entry = emit.mir.instructions.items(.data)[inst].got_entry;
|
||||
@ -1058,7 +1293,7 @@ fn mirDbgLine(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
|
||||
const tag = emit.mir.instructions.items(.tag)[inst];
|
||||
assert(tag == .dbg_line);
|
||||
const payload = emit.mir.instructions.items(.data)[inst].payload;
|
||||
const dbg_line_column = emit.mir.extraData(Mir.DbgLineColumn, payload).data;
|
||||
const dbg_line_column = Mir.extraData(emit.mir.extra, Mir.DbgLineColumn, payload).data;
|
||||
try emit.dbgAdvancePCAndLine(dbg_line_column.line, dbg_line_column.column);
|
||||
}
|
||||
|
||||
@ -1143,7 +1378,7 @@ fn mirArgDbgInfo(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
|
||||
const tag = emit.mir.instructions.items(.tag)[inst];
|
||||
assert(tag == .arg_dbg_info);
|
||||
const payload = emit.mir.instructions.items(.data)[inst].payload;
|
||||
const arg_dbg_info = emit.mir.extraData(Mir.ArgDbgInfo, payload).data;
|
||||
const arg_dbg_info = Mir.extraData(emit.mir.extra, Mir.ArgDbgInfo, payload).data;
|
||||
const mcv = emit.mir.function.args[arg_dbg_info.arg_index];
|
||||
try emit.genArgDbgInfo(arg_dbg_info.air_inst, mcv);
|
||||
}
|
||||
@ -1206,3 +1441,384 @@ fn addDbgInfoTypeReloc(emit: *Emit, ty: Type) !void {
|
||||
.none => {},
|
||||
}
|
||||
}
|
||||
|
||||
const Mock = struct {
|
||||
const gpa = testing.allocator;
|
||||
|
||||
mir_instructions: std.MultiArrayList(Mir.Inst) = .{},
|
||||
mir_extra: std.ArrayList(u32),
|
||||
code: std.ArrayList(u8),
|
||||
|
||||
fn init() Mock {
|
||||
return .{
|
||||
.mir_extra = std.ArrayList(u32).init(gpa),
|
||||
.code = std.ArrayList(u8).init(gpa),
|
||||
};
|
||||
}
|
||||
|
||||
fn deinit(self: *Mock) void {
|
||||
self.mir_instructions.deinit(gpa);
|
||||
self.mir_extra.deinit();
|
||||
self.code.deinit();
|
||||
}
|
||||
|
||||
fn addInst(self: *Mock, inst: Mir.Inst) error{OutOfMemory}!Mir.Inst.Index {
|
||||
try self.mir_instructions.ensureUnusedCapacity(gpa, 1);
|
||||
const result_index = @intCast(Air.Inst.Index, self.mir_instructions.len);
|
||||
self.mir_instructions.appendAssumeCapacity(inst);
|
||||
return result_index;
|
||||
}
|
||||
|
||||
fn addExtra(self: *Mock, extra: anytype) Allocator.Error!u32 {
|
||||
const fields = std.meta.fields(@TypeOf(extra));
|
||||
try self.mir_extra.ensureUnusedCapacity(fields.len);
|
||||
return self.addExtraAssumeCapacity(extra);
|
||||
}
|
||||
|
||||
fn addExtraAssumeCapacity(self: *Mock, extra: anytype) u32 {
|
||||
const fields = std.meta.fields(@TypeOf(extra));
|
||||
const result = @intCast(u32, self.mir_extra.items.len);
|
||||
inline for (fields) |field| {
|
||||
self.mir_extra.appendAssumeCapacity(switch (field.field_type) {
|
||||
u32 => @field(extra, field.name),
|
||||
i32 => @bitCast(u32, @field(extra, field.name)),
|
||||
else => @compileError("bad field type"),
|
||||
});
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
fn testEmitSingleSuccess(
|
||||
self: *Mock,
|
||||
mir_inst: Mir.Inst,
|
||||
expected_enc: []const u8,
|
||||
assembly: []const u8,
|
||||
) !void {
|
||||
const code_index = self.code.items.len;
|
||||
const mir_index = try self.addInst(mir_inst);
|
||||
switch (mir_inst.tag) {
|
||||
.mov => try mirMovImpl(
|
||||
self.mir_instructions.slice(),
|
||||
self.mir_extra.items,
|
||||
mir_index,
|
||||
&self.code,
|
||||
),
|
||||
else => unreachable,
|
||||
}
|
||||
const code_len = if (self.code.items[code_index..].len >= expected_enc.len)
|
||||
expected_enc.len
|
||||
else
|
||||
self.code.items.len - code_index;
|
||||
try expectEqualHexStrings(expected_enc, self.code.items[code_index..][0..code_len], assembly);
|
||||
}
|
||||
|
||||
fn testEmitSingleError(self: *Mock, mir_inst: Mir.Inst, err: EmitError) !void {
|
||||
const index = try self.addInst(mir_inst);
|
||||
const res = switch (mir_inst.tag) {
|
||||
.mov => mirMovImpl(
|
||||
self.mir_instructions.slice(),
|
||||
self.mir_extra.items,
|
||||
index,
|
||||
&self.code,
|
||||
),
|
||||
else => unreachable,
|
||||
};
|
||||
try testing.expectError(err, res);
|
||||
}
|
||||
};
|
||||
|
||||
fn expectEqualHexStrings(expected: []const u8, given: []const u8, assembly: []const u8) !void {
|
||||
assert(expected.len > 0);
|
||||
if (mem.eql(u8, expected, given)) return;
|
||||
const expected_fmt = try std.fmt.allocPrint(testing.allocator, "{x}", .{std.fmt.fmtSliceHexLower(expected)});
|
||||
defer testing.allocator.free(expected_fmt);
|
||||
const given_fmt = try std.fmt.allocPrint(testing.allocator, "{x}", .{std.fmt.fmtSliceHexLower(given)});
|
||||
defer testing.allocator.free(given_fmt);
|
||||
const idx = mem.indexOfDiff(u8, expected_fmt, given_fmt).?;
|
||||
var padding = try testing.allocator.alloc(u8, idx + 5);
|
||||
defer testing.allocator.free(padding);
|
||||
mem.set(u8, padding, ' ');
|
||||
std.debug.print("\nASM: {s}\nEXP: {s}\nGIV: {s}\n{s}^ -- first differing byte\n", .{
|
||||
assembly,
|
||||
expected_fmt,
|
||||
given_fmt,
|
||||
padding,
|
||||
});
|
||||
return error.TestFailed;
|
||||
}
|
||||
|
||||
test "mov dst_reg, src_reg" {
|
||||
var mock = Mock.init();
|
||||
defer mock.deinit();
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .rbp, .reg2 = .rsp }).encode(),
|
||||
.data = undefined,
|
||||
}, "\x48\x89\xe5", "mov rbp, rsp");
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .r12, .reg2 = .rax }).encode(),
|
||||
.data = undefined,
|
||||
}, "\x49\x89\xc4", "mov r12, rax");
|
||||
try mock.testEmitSingleError(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .r12, .reg2 = .eax }).encode(),
|
||||
.data = undefined,
|
||||
}, error.OperandSizeMismatch);
|
||||
try mock.testEmitSingleError(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .r12d, .reg2 = .rax }).encode(),
|
||||
.data = undefined,
|
||||
}, error.OperandSizeMismatch);
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .r12d, .reg2 = .eax }).encode(),
|
||||
.data = undefined,
|
||||
}, "\x41\x89\xc4", "mov r12d, eax");
|
||||
|
||||
// TODO mov r12b, ah requires a codepath without REX prefix
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .r12b, .reg2 = .al }).encode(),
|
||||
.data = undefined,
|
||||
}, "\x41\x88\xc4", "mov r12b, al");
|
||||
}
|
||||
|
||||
test "mov dst_reg, imm" {
|
||||
var mock = Mock.init();
|
||||
defer mock.deinit();
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .rcx }).encode(),
|
||||
.data = .{ .imm = 0x10 },
|
||||
}, "\x48\xc7\xc1\x10\x00\x00\x00", "mov rcx, 0x10");
|
||||
|
||||
// TODO we are wasting one byte here: this could be encoded as OI with the encoding opc + rd, imm8/16/32
|
||||
// b9 10 00 00 00
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .ecx }).encode(),
|
||||
.data = .{ .imm = 0x10 },
|
||||
}, "\xc7\xc1\x10\x00\x00\x00", "mov ecx, 0x10");
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .cx }).encode(),
|
||||
.data = .{ .imm = 0x10 },
|
||||
}, "\x66\xc7\xc1\x10\x00", "mov cx, 0x10");
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .r11w }).encode(),
|
||||
.data = .{ .imm = 0x10 },
|
||||
}, "\x66\x41\xC7\xC3\x10\x00", "mov r11w, 0x10");
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .cl }).encode(),
|
||||
.data = .{ .imm = 0x10 },
|
||||
}, "\xc6\xc1\x10", "mov cl, 0x10");
|
||||
try mock.testEmitSingleError(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .cx }).encode(),
|
||||
.data = .{ .imm = 0x10000000 },
|
||||
}, error.OperandSizeMismatch);
|
||||
try mock.testEmitSingleError(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .cl }).encode(),
|
||||
.data = .{ .imm = 0x1000 },
|
||||
}, error.OperandSizeMismatch);
|
||||
}
|
||||
|
||||
test "mov dst_reg, [imm32]" {
|
||||
var mock = Mock.init();
|
||||
defer mock.deinit();
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .rcx, .flags = 0b01 }).encode(),
|
||||
.data = .{ .imm = 0x10 },
|
||||
}, "\x48\x8B\x0C\x25\x10\x00\x00\x00", "mov rcx, [0x10]");
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .r11, .flags = 0b01 }).encode(),
|
||||
.data = .{ .imm = 0x10 },
|
||||
}, "\x4C\x8B\x1C\x25\x10\x00\x00\x00", "mov r11, [0x10]");
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .r11d, .flags = 0b01 }).encode(),
|
||||
.data = .{ .imm = 0x10 },
|
||||
}, "\x44\x8B\x1C\x25\x10\x00\x00\x00", "mov r11d, [0x10]");
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .r11w, .flags = 0b01 }).encode(),
|
||||
.data = .{ .imm = 0x10 },
|
||||
}, "\x66\x44\x8B\x1C\x25\x10\x00\x00\x00", "mov r11w, [0x10]");
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .r11b, .flags = 0b01 }).encode(),
|
||||
.data = .{ .imm = 0x10 },
|
||||
}, "\x44\x8A\x1C\x25\x10\x00\x00\x00", "mov r11b, [0x10]");
|
||||
}
|
||||
|
||||
test "mov dst_reg, [src_reg + imm]" {
|
||||
var mock = Mock.init();
|
||||
defer mock.deinit();
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .rcx, .reg2 = .rbp, .flags = 0b01 }).encode(),
|
||||
.data = .{ .imm = 0x10 },
|
||||
}, "\x48\x8B\x4D\x10", "mov rcx, [rbp + 0x10]");
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .rcx, .reg2 = .rbp, .flags = 0b01 }).encode(),
|
||||
.data = .{ .imm = 0x10000000 },
|
||||
}, "\x48\x8B\x8D\x00\x00\x00\x10", "mov rcx, [rbp + 0x10000000]");
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .r11b, .reg2 = .rbp, .flags = 0b01 }).encode(),
|
||||
.data = .{ .imm = 0x10 },
|
||||
}, "\x44\x8A\x5D\x10", "mov r11b, [rbp + 0x10]");
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .r11w, .reg2 = .rbp, .flags = 0b01 }).encode(),
|
||||
.data = .{ .imm = 0x10000000 },
|
||||
}, "\x66\x44\x8B\x9D\x00\x00\x00\x10", "mov r11w, [rbp + 0x10000000]");
|
||||
}
|
||||
|
||||
test "mov [dst_reg + 0], imm" {
|
||||
var mock = Mock.init();
|
||||
defer mock.deinit();
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .r11, .flags = 0b10 }).encode(),
|
||||
.data = .{ .imm = 0x10 },
|
||||
}, "\x41\xC7\x03\x10\x00\x00\x00", "mov dword ptr [r11 + 0], 0x10");
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .rax, .flags = 0b10 }).encode(),
|
||||
.data = .{ .imm = 0x10000000 },
|
||||
}, "\xC7\x00\x00\x00\x00\x10", "mov dword ptr [rax + 0], 0x10000000");
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .rax, .flags = 0b10 }).encode(),
|
||||
.data = .{ .imm = 0x1000 },
|
||||
}, "\xC7\x00\x00\x10\x00\x00", "mov dword ptr [rax + 0], 0x1000");
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .rax, .flags = 0b10 }).encode(),
|
||||
.data = .{ .imm = 0x10 },
|
||||
}, "\xC7\x00\x10\x00\x00\x00", "mov dword ptr [rax + 0], 0x10");
|
||||
try mock.testEmitSingleError(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .eax, .flags = 0b10 }).encode(),
|
||||
.data = .{ .imm = 0x10 },
|
||||
}, error.OperandSizeMismatch);
|
||||
}
|
||||
|
||||
test "mov [dst_reg + imm32], src_reg" {
|
||||
var mock = Mock.init();
|
||||
defer mock.deinit();
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .rbp, .reg2 = .r11, .flags = 0b10 }).encode(),
|
||||
.data = .{ .imm = 0x10 },
|
||||
}, "\x4c\x89\x5d\x10", "mov qword ptr [rbp + 0x10], r11");
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .rbp, .reg2 = .r11d, .flags = 0b10 }).encode(),
|
||||
.data = .{ .imm = 0x10 },
|
||||
}, "\x44\x89\x5d\x10", "mov dword ptr [rbp + 0x10], r11d");
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .rbp, .reg2 = .r11w, .flags = 0b10 }).encode(),
|
||||
.data = .{ .imm = 0x10 },
|
||||
}, "\x66\x44\x89\x5d\x10", "mov word ptr [rbp + 0x10], r11w");
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .rbp, .reg2 = .r11b, .flags = 0b10 }).encode(),
|
||||
.data = .{ .imm = 0x10 },
|
||||
}, "\x44\x88\x5d\x10", "mov byte ptr [rbp + 0x10], r11b");
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .r11, .reg2 = .rax, .flags = 0b10 }).encode(),
|
||||
.data = .{ .imm = 0x10 },
|
||||
}, "\x49\x89\x43\x10", "mov qword ptr [r11 + 0x10], rax");
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .r11, .reg2 = .eax, .flags = 0b10 }).encode(),
|
||||
.data = .{ .imm = 0x10 },
|
||||
}, "\x41\x89\x43\x10", "mov dword ptr [r11 + 0x10], eax");
|
||||
try mock.testEmitSingleError(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .r11w, .reg2 = .ax, .flags = 0b10 }).encode(),
|
||||
.data = .{ .imm = 0x10 },
|
||||
}, error.OperandSizeMismatch);
|
||||
}
|
||||
|
||||
test "mov [dst_reg + imm32], imm32" {
|
||||
var mock = Mock.init();
|
||||
defer mock.deinit();
|
||||
{
|
||||
const payload = try mock.addExtra(Mir.ImmPair{
|
||||
.dest_off = 0x10,
|
||||
.operand = 0x20000000,
|
||||
});
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .rbp, .flags = 0b11 }).encode(),
|
||||
.data = .{ .payload = payload },
|
||||
}, "\xC7\x45\x10\x00\x00\x00\x20", "mov dword ptr [rbp + 0x10], 0x20000000");
|
||||
}
|
||||
{
|
||||
const payload = try mock.addExtra(Mir.ImmPair{
|
||||
.dest_off = 0x10,
|
||||
.operand = 0x2000,
|
||||
});
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .rbp, .flags = 0b11 }).encode(),
|
||||
.data = .{ .payload = payload },
|
||||
}, "\xC7\x45\x10\x00\x20\x00\x00", "mov dword ptr [rbp + 0x10], 0x2000");
|
||||
}
|
||||
{
|
||||
const payload = try mock.addExtra(Mir.ImmPair{
|
||||
.dest_off = 0x10,
|
||||
.operand = 0x20,
|
||||
});
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .rbp, .flags = 0b11 }).encode(),
|
||||
.data = .{ .payload = payload },
|
||||
}, "\xc7\x45\x10\x20\x00\x00\x00", "mov dword ptr [rbp + 0x10], 0x20");
|
||||
}
|
||||
{
|
||||
const payload = try mock.addExtra(Mir.ImmPair{
|
||||
.dest_off = 0x10,
|
||||
.operand = 0x20000000,
|
||||
});
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .r11, .flags = 0b11 }).encode(),
|
||||
.data = .{ .payload = payload },
|
||||
}, "\x41\xC7\x43\x10\x00\x00\x00\x20", "mov dword ptr [r11 + 0x10], 0x20000000");
|
||||
}
|
||||
{
|
||||
const payload = try mock.addExtra(Mir.ImmPair{
|
||||
.dest_off = 0x10000000,
|
||||
.operand = 0x20000000,
|
||||
});
|
||||
try mock.testEmitSingleSuccess(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .r11, .flags = 0b11 }).encode(),
|
||||
.data = .{ .payload = payload },
|
||||
}, "\x41\xC7\x83\x00\x00\x00\x10\x00\x00\x00\x20", "mov dword ptr [r11 + 0x10], 0x20000000");
|
||||
}
|
||||
{
|
||||
const payload = try mock.addExtra(Mir.ImmPair{
|
||||
.dest_off = 0x10,
|
||||
.operand = 0x20,
|
||||
});
|
||||
try mock.testEmitSingleError(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{ .reg1 = .r11d, .flags = 0b11 }).encode(),
|
||||
.data = .{ .payload = payload },
|
||||
}, error.OperandSizeMismatch);
|
||||
}
|
||||
}
|
||||
|
||||
@ -136,10 +136,24 @@ pub const Inst = struct {
|
||||
cmp_scale_src,
|
||||
cmp_scale_dst,
|
||||
cmp_scale_imm,
|
||||
|
||||
/// ops flags: form:
|
||||
/// 0b00 reg1, reg2 (MR)
|
||||
/// 0b00 reg1, imm32
|
||||
/// 0b01 reg1, [reg2 + imm32]
|
||||
/// 0b01 reg1, [ds:imm32]
|
||||
/// 0b10 [reg1 + imm32], reg2
|
||||
/// 0b10 [reg1 + 0], imm32
|
||||
/// 0b11 [reg1 + imm32], imm32
|
||||
/// 0b11 reg1, reg2 (RM)
|
||||
/// Notes:
|
||||
/// * If reg2 is `none` then it means Data field `imm` is used as the immediate.
|
||||
/// * When two imm32 values are required, Data field `payload` points at `ImmPair`.
|
||||
mov,
|
||||
mov_scale_src,
|
||||
mov_scale_dst,
|
||||
mov_scale_imm,
|
||||
|
||||
lea,
|
||||
lea_scale_src,
|
||||
lea_scale_dst,
|
||||
@ -292,6 +306,7 @@ pub const Inst = struct {
|
||||
/// Another instruction.
|
||||
inst: Index,
|
||||
/// A 32-bit immediate value.
|
||||
/// TODO we should add support for 16- and 8-bit immediate values.
|
||||
imm: i32,
|
||||
/// An extern function.
|
||||
/// Index into the linker's string table.
|
||||
@ -378,14 +393,14 @@ pub const Ops = struct {
|
||||
}
|
||||
};
|
||||
|
||||
pub fn extraData(mir: Mir, comptime T: type, index: usize) struct { data: T, end: usize } {
|
||||
pub fn extraData(mir_extra: []const u32, comptime T: type, index: usize) struct { data: T, end: usize } {
|
||||
const fields = std.meta.fields(T);
|
||||
var i: usize = index;
|
||||
var result: T = undefined;
|
||||
inline for (fields) |field| {
|
||||
@field(result, field.name) = switch (field.field_type) {
|
||||
u32 => mir.extra[i],
|
||||
i32 => @bitCast(i32, mir.extra[i]),
|
||||
u32 => mir_extra[i],
|
||||
i32 => @bitCast(i32, mir_extra[i]),
|
||||
else => @compileError("bad field type"),
|
||||
};
|
||||
i += 1;
|
||||
|
||||
@ -481,7 +481,7 @@ fn mirArith(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: any
|
||||
0b11 => {
|
||||
if (ops.reg2 == .none) {
|
||||
const payload = print.mir.instructions.items(.data)[inst].payload;
|
||||
const imm_pair = print.mir.extraData(Mir.ImmPair, payload).data;
|
||||
const imm_pair = Mir.extraData(print.mir.extra, Mir.ImmPair, payload).data;
|
||||
try w.print("[{s} + {d}], {d}", .{ @tagName(ops.reg1), imm_pair.dest_off, imm_pair.operand });
|
||||
}
|
||||
try w.writeAll("TODO");
|
||||
@ -516,7 +516,7 @@ fn mirArithScaleImm(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index
|
||||
const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
|
||||
const scale = ops.flags;
|
||||
const payload = print.mir.instructions.items(.data)[inst].payload;
|
||||
const imm_pair = print.mir.extraData(Mir.ImmPair, payload).data;
|
||||
const imm_pair = Mir.extraData(print.mir.extra, Mir.ImmPair, payload).data;
|
||||
try w.print("{s} [{s} + {d}*rcx + {d}], {d}\n", .{ @tagName(tag), @tagName(ops.reg1), scale, imm_pair.dest_off, imm_pair.operand });
|
||||
}
|
||||
|
||||
@ -528,7 +528,7 @@ fn mirMovabs(print: *const Print, inst: Mir.Inst.Index, w: anytype) !void {
|
||||
const is_64 = ops.reg1.size() == 64;
|
||||
const imm: i128 = if (is_64) blk: {
|
||||
const payload = print.mir.instructions.items(.data)[inst].payload;
|
||||
const imm64 = print.mir.extraData(Mir.Imm64, payload).data;
|
||||
const imm64 = Mir.extraData(print.mir.extra, Mir.Imm64, payload).data;
|
||||
break :blk imm64.decode();
|
||||
} else print.mir.instructions.items(.data)[inst].imm;
|
||||
if (ops.flags == 0b00) {
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user