Luuk de Gram
6ae898b244
wasm: more f16 support and cleanup of intrinsics
...
`genFunctype` now accepts calling convention, param types, and return type
as part of its function signature rather than `fnData`. This means
we no longer have to create a dummy for our intrinsic call abstraction.
This also adds support for f16 division and builtins such as `@ceil` & more.
2022-06-24 08:12:17 +02:00
Luuk de Gram
9015efe405
wasm: Implement @mulAdd for f16
...
Implements `@mulAdd` for floats with bitsize 16, where it generates
a call into compiler-rt's `fmaf` function. Note that arguments
for fmaf are different in order than `@mulAdd`.
2022-06-24 08:12:17 +02:00
Luuk de Gram
5ebaf49ebb
wasm: Implement basic f16 support
...
This implements binary operations and comparisons
for floats with bitsize 16. It does this by calling into
compiler-rt to first extend the float to 32 bits, perform the operation,
and then finally truncate back to 16 bits. When loading and storing the f16,
we do this as an unsigned 16bit integer.
2022-06-24 08:12:17 +02:00
Luuk de Gram
8d03e4fc6b
link: Implement API to get global symbol index
2022-06-24 08:12:17 +02:00
Luuk de Gram
359b61aec3
wasm: Create compiler-rt symbols and lowering
...
Implements the creation of an undefined symbol for a compiler-rt intrinsic.
Also implements the building of the function call to said compiler-rt intrinsic.
2022-06-24 08:12:17 +02:00
Luuk de Gram
a50147bfff
wasm: fixes for signed saturation
2022-06-19 17:26:44 +02:00
Luuk de Gram
05600a6d84
wasm: saturating shift-left for signed integers
2022-06-19 15:50:03 +02:00
Luuk de Gram
53831442ef
wasm: saturating shift-left for unsigned integers
2022-06-19 14:30:17 +02:00
Luuk de Gram
ce5d934f5f
wasm: saturating add and sub for signed integers
2022-06-19 14:30:17 +02:00
Luuk de Gram
fcd4280a8c
wasm: implement saturating add, sub for unsigned
...
Implements +| and -| for unsigned integers <= 64 bits.
2022-06-19 14:30:13 +02:00
Andrew Kelley
ffa700ee58
Merge pull request #11837 from Vexu/stage2
...
Fix (nearly) all stage2 crashes when testing stdlib
2022-06-12 17:45:57 -04:00
Veikka Tuominen
0333ff4476
stage2: make error{} the same size as anyerror
...
Having `error{}` be a zero bit type causes issues when it interracts
with empty inferred error sets which are the same size as `anyerror`.
2022-06-11 23:49:33 +03:00
Luuk de Gram
13123afedb
wasm: implement @ceil, @floor and @trunc
2022-06-11 19:38:00 +02:00
Luuk de Gram
f05e09a0cf
wasm: optimize & simplify sign extension
...
Rather than storing all the shifts in temporaries, we perform the correct
shifting without temporaries. This makes the runtime code more performant
and also the backend code is simplified as we have a singular abstraction.
2022-06-11 19:38:00 +02:00
Luuk de Gram
18afcc34c6
wasm: implement @divFloor for signed integers
2022-06-11 19:38:00 +02:00
Luuk de Gram
3011ef2d82
wasm: signed integer division (non-floor)
...
Implements the non-floor variants of signed integer division.
2022-06-11 19:38:00 +02:00
Luuk de Gram
9b84f29503
wasm: support all @div{trunc/floor/exact} ops
...
This does however not support floats of bitsizes
different than 32 or 64. f16, f80, f126 will require
support for compiler-rt and are out-of-scope for this commit.
Signed integers are currently not supported either.
2022-06-11 19:38:00 +02:00
Luuk de Gram
180baa0546
wasm:@byteSwap for 24 bit integers
2022-06-11 19:38:00 +02:00
Luuk de Gram
bc499de328
wasm: implement @byteSwap for 16/32bit integers
2022-06-11 19:38:00 +02:00
Andrew Kelley
bac132bc8f
introduce std.debug.Trace
...
And use it to debug a LazySrcLoc in stage2 that is set to a bogus value.
The actual fix in this commit is:
```diff
- try sema.emitBackwardBranch(&child_block, call_src);
+ try sema.emitBackwardBranch(block, call_src);
```
2022-06-09 15:37:16 -07:00
joachimschmidt557
61844b6bd4
stage2 AArch64: introduce MCValue.condition_flags
...
Follows 9747303d16dfca61316a292d1e05ac901191e3a3 for AArch64
2022-06-07 23:34:42 -04:00
Jakub Konka
3cb3873382
Merge pull request #11814 from ziglang/x64-stack-handling
...
x64: improves stack handling, fixes a heisenbug, adds micro-optimisations
2022-06-07 23:22:20 +02:00
Jakub Konka
6c59aa9e02
Merge pull request #11806 from koachan/sparc64-codegen
...
stage2: sparc64: Some more Air lowerings
2022-06-07 21:24:56 +02:00
Jakub Konka
27dad11ef1
x64: remove outdated TODO comment
2022-06-07 21:05:11 +02:00
Jakub Konka
76ad7af4d8
x64: pull common codepath between store and genSetStack into a helper
2022-06-07 19:33:43 +02:00
Jakub Konka
03068ce6a6
x64: clean up store helper
2022-06-07 19:33:43 +02:00
Jakub Konka
0c72760454
x64: optimise element offset calculation if dealing with immediates
...
If `index` MCValue is actually an immediate, we can calculate offset
directly at "comptime" rather than at runtime.
2022-06-07 19:33:43 +02:00
Jakub Konka
fc015231ad
x64: account for non-pow-two stores via register deref
...
In this case, we need to proceed rather carefully to avoid writing
containing register width rather than the precise amount of bytes.
2022-06-07 19:33:43 +02:00
Jakub Konka
117f9f69e7
x64: simplify saving registers to stack in prologue
2022-06-07 19:33:40 +02:00
Andrew Kelley
d1bfc83774
Merge pull request #11783 from ziglang/stage2-try
...
introduce a "try" ZIR and AIR instruction
2022-06-06 19:01:39 -04:00
joachimschmidt557
8ca6dc33d1
stage2 AArch64: implement try AIR instruction
2022-06-06 21:27:36 +02:00
Jakub Konka
e05de31a5f
dwarf: fix incorrect type reloc for unions
...
Split type relocs into two kinds: local and global. Global relocs
use a global type resolver and calculate offset to the existing
definition of a type abbreviation.
Local relocs use offset in the abbrev section of the containing
atom plus addend to generate a local relocation.
2022-06-06 19:58:51 +02:00
Koakuma
ec7f2a105f
stage2: sparc64: Implement airPtrElemPtr
2022-06-06 21:17:09 +07:00
Koakuma
f6eb83c91c
stage2: sparc64: Implement airArrayToSlice
2022-06-06 21:17:09 +07:00
Koakuma
f87dd285bb
stage2: sparc64: binOp/mul: Use template from add
2022-06-06 20:34:53 +07:00
Koakuma
31f24dbc55
stage2: sparc64: Implement airWrapErrUnionErr
2022-06-06 20:34:53 +07:00
Koakuma
c00d493a00
stage2: sparc64: Add some notes about stack space allocation
2022-06-06 20:34:53 +07:00
Koakuma
5d61f32887
stage2: sparc64: Implement airSlice
2022-06-06 20:34:53 +07:00
Koakuma
8b70abfcc6
stage2: sparc64: Fix & optimize 64-bit truncRegister
2022-06-06 20:34:53 +07:00
Koakuma
4d50e52c37
stage2: sparc64: Implement SPARCv9 xor, xnor, & not
2022-06-06 20:34:53 +07:00
Koakuma
97f9bf7e90
stage2: sparc64: Add BPr relocation to performReloc
2022-06-06 20:34:53 +07:00
Koakuma
23150de9c4
stage2: sparc64: Implement airNot
2022-06-06 20:34:53 +07:00
Koakuma
9ad74b6087
stage2: sparc64: Implement SPARCv9 addcc and movcc
2022-06-06 20:34:53 +07:00
Koakuma
97c43afefe
stage2: sparc64: Spill CCR before doing calls
2022-06-06 20:34:53 +07:00
Koakuma
2dfe307d60
stage2: sparc64: Some bookkeeping fixes
2022-06-06 20:34:53 +07:00
Koakuma
89b4195c69
stage2: sparc64: Account for delay slot in airBlock
2022-06-06 20:34:53 +07:00
Koakuma
3220e0b61c
stage2: sparc64: Proper handling of compare flags
2022-06-06 20:34:53 +07:00
Koakuma
9db81fee5d
stage2: sparc64: Implement airStructFieldVal
2022-06-06 20:34:53 +07:00
Koakuma
3d662cfaf4
stage2: sparc64: Implement airAddSubOverflow
2022-06-06 20:34:53 +07:00
Koakuma
093332c02e
stage2: sparc64: Implement condition code spilling
2022-06-06 20:34:53 +07:00
