149 Commits

Author SHA1 Message Date
Andrew Kelley
615d45da77 Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgen
Conflicts:
 * src/codegen/spirv.zig
 * src/link/SpirV.zig

We're going to want to improve the stage2 test harness to print
the source file name when a compile error occurs otherwise std lib
contributors are going to see some confusing CI failures when they cause
stage2 AstGen compile errors.
2021-05-17 19:30:38 -07:00
joachimschmidt557
65cee0b3fd stage2 ARM: correct spilling in genArmMul as well 2021-05-17 17:18:01 -04:00
Andrew Kelley
597082adf4 Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgen
Conflicts:
 * build.zig
 * src/Compilation.zig
 * src/codegen/spirv/spec.zig
 * src/link/SpirV.zig
 * test/stage2/darwin.zig
   - this one might be problematic; start.zig looks for `main` in the
     root source file, not `_main`. Not sure why there is an underscore
     there in master branch.
2021-05-15 21:44:38 -07:00
Andrew Kelley
07606d12da stage2: remove SPU Mark II backend
As it stands, the backend is incomplete, and there is no active contributor,
making it dead weight.

However, anyone is free to resurrect this backend at any time.
2021-05-15 21:25:42 -07:00
Andrew Kelley
dc036f5b6f codegen: implement const value rendering for ints <= 64 bits 2021-05-15 21:00:15 -07:00
joachimschmidt557
8b4e91e18c stage2 register manager: clean up API and add more unit tests 2021-05-14 15:12:33 -04:00
Andrew Kelley
c9cc09a3bf Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgen
Conflicts:
 * lib/std/os/linux.zig
 * lib/std/os/windows/bits.zig
 * src/Module.zig
 * src/Sema.zig
 * test/stage2/test.zig

Mainly I wanted Jakub's new macOS code for respecting stack size, since
we now depend on it for debug builds able to pass one of the test cases
for recursive comptime function calls with `@setEvalBranchQuota`.

The conflicts were all trivial.
2021-05-12 16:41:20 -07:00
joachimschmidt557
d211dc37c8 stage2 ARM: Overhaul of genArmBinOp 2021-05-09 08:48:58 +02:00
Andrew Kelley
b88d381dec
Merge pull request #8474 from gracefuu/grace/encode-instruction
stage2 x86_64: encoding helpers, fix bugs
2021-05-09 01:36:51 -04:00
Andrew Kelley
eadcefc124 stage2: dbg_stmt ZIR instructions have line/col
instead of node indexes.

 * AstGen: dbg_stmt instructions now have line and column indexes,
   relative to the parent declaration. This allows codegen to emit debug
   info without having the source bytes, tokens, or AST nodes loaded
   in memory.
 * ZIR: each decl has the absolute line number. This allows computing
   line numbers from offsets without consulting source code bytes.

Memory management: creating a function definition does not prematurely
set the Decl arena. Instead the function is allocated with the general
purpose allocator.

Codegen no longer looks at source code bytes for any reason. They can
remain unloaded from disk.
2021-05-01 21:57:52 -07:00
Andrew Kelley
0c71d2fdc1 stage2: implement semantic analysis for functions and global vars
* AstGen: add missing `break_inline` for comptime blocks.
 * Module: call getTree() in byteOffset(). This generates the AST when
   using cached ZIR and compile errors need to be reported.
 * Scope.File: distinguish between successful ZIR generation and AIR
   generation (when Decls in scope have been scanned).
   - `semaFile` correctly avoids doing work twice.
 * Implement first pass at `lookupInNamespace`. It has various TODOs
   left, such as `usingnamespace`, and setting up Decl dependencies.
2021-04-28 22:43:26 -07:00
Andrew Kelley
f86469bc5e stage2: semaDecl properly analyzes the decl block
Also flattened out Decl TypedValue fields into
ty, val, has_tv
and add relevant fields to Decl for alignment and link section.
2021-04-28 16:57:01 -07:00
Andrew Kelley
df24ce52b1 Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgen
In particular I wanted to take advantage of the new hex float parsing
code.
2021-04-28 14:57:38 -07:00
joachimschmidt557
3a55cda14d stage2 register manager: Use an array instead of a hashmap for tracking
allocated registers
2021-04-25 13:20:53 -04:00
Andrew Kelley
e86cee258c Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgen
In particular I wanted the change that makes `suspend;` illegal in the
parser.
2021-04-24 10:44:41 -07:00
jacob gw
6b944492b5 stage2: fix compile error in codegen 2021-04-20 17:08:05 -04:00
Andrew Kelley
4630e3891c AstGen: implement inline asm output 2021-04-19 18:44:59 -07:00
joachimschmidt557
fbda9991f4 stage2 codegen: Fix silent bug in reuseOperand 2021-04-17 20:57:26 -04:00
gracefu
cfeb412a42
stage2 x86_64: fix incorrect comment in genX8664BinMath
Co-authored-by: joachimschmidt557 <joachim.schmidt557@outlook.com>
2021-04-16 15:21:17 +08:00
gracefu
dc13662725
stage2 x86_64: force 64 bit mode when loading address of GOT
Co-authored-by: joachimschmidt557 <joachim.schmidt557@outlook.com>
2021-04-16 15:21:17 +08:00
gracefu
1e63e8d8b6
stage2 x86_64: fix codegen ensureCapacity bug for function calls
Co-authored-by: joachimschmidt557 <joachim.schmidt557@outlook.com>
2021-04-16 15:21:17 +08:00
gracefu
62e755623f
stage2 x86_64: bugfix abi_size == 64 should be abi_size == 8 2021-04-16 15:21:17 +08:00
gracefu
b004c3da15
stage2 x86_64: try to fix RIP-relative offset to GOT for macho 2021-04-16 15:21:17 +08:00
gracefu
0409f9e024
stage2 x86_64: simplify inst encoder to a set of dumb helper fns 2021-04-16 15:21:17 +08:00
gracefu
c4b83ea021
stage2 x86_64: implement integer mul
This was also an experiment to see if it were easier to implement a new
feature when using the instruction encoder.

Verdict: It's not that much easier, but I think it's certainly much more
readable, because the description of the Instruction annotates what each
field means. Right now, precise knowledge of x86_64 instructions is
still required because things like when to set the 64-bit flag, how to
read x86_64 instruction references, etc. are still not automatically
done for you.

In the future, this interface might make it sligtly easier to write an
assembler for x86_64, by abstracting the bit-fiddling aspects of
instruction encoding.
2021-04-16 15:21:17 +08:00
gracefu
5bd464e386
stage2 x86_64: use abi size to determine 64-bit operation
From my very cursory reading, it seems that the register manager doesn't
distinguish between registers that are physically the same but have
different sizes.

In that case, this means that during codegen, we can't rely on
`reg.size()` when determining the width of the operations we have to
perform. Instead, we must use some form of `ty.abiSize(self.target.*)`
to determine the size of the type we're operating with. If this size is
64 bits, then we should enable 64-bit operation.

This fixed a bug in the codegen for spilling instructions, which was
overwriting the previous stack entry with zeroes. See the modified test
case in this commit.
2021-04-16 15:21:17 +08:00
gracefu
36df1526da
stage2 x86_64: refactor codegen to use inst encoder
There are parts of it that I didn't modify because the byte
representation was important (e.g. we need to know what the exact
byte position where we store the address into the offset table is)
2021-04-16 15:21:17 +08:00
Andrew Kelley
f458192e56 stage2: entry point via std lib and proper updated file detection
Instead of Module setting up the root_scope with the root source file,
instead, Module relies on the package table graph being set up properly,
and inside `update()`, it does the equivalent of `_ = @import("std");`.
This, in term, imports start.zig, which has the logic to call main (or
not). `Module` no longer has `root_scope` - the root source file is no
longer special, it's just in the package table mapped to "root".

I also went ahead and implemented proper detection of updated files.
mtime, inode, size, and source hash are kept in `Scope.File`.
During an update, iterate over `import_table` and stat each file to find
out which ones are updated.

The source hash is redundant with the source hash used by the struct
decl that corresponds to the file, so it should be removed in a future
commit before merging the branch.

 * AstGen: add "previously declared here" notes for variables shadowing
   decls.
 * Parse imports as structs. Module now calls `AstGen.structDeclInner`,
   which is called by `AstGen.containerDecl`.
   - `importFile` is a bit kludgy with how it handles the top level Decl
     that kinda gets merged into the struct decl at the end of the
     function. Be on the look out for bugs related to that as well as
     possibly cleaner ways to implement this.
 * Module: factor out lookupDeclName into lookupIdentifier and lookupNa
 * Rename `Scope.Container` to `Scope.Namespace`.
 * Delete some dead code.

This branch won't work until `usingnamespace` is implemented because it
relies on `@import("builtin").OutputMode` and `OutputMode` comes from a
`usingnamespace`.
2021-04-15 19:06:39 -07:00
joachimschmidt557
4fe575f47b
stage2 ARM: Add fibonacci test 2021-04-11 10:19:36 +02:00
joachimschmidt557
a6ddc12b33
stage2 codegen: Set MCValue of register arguments to their stack copy 2021-04-11 10:19:35 +02:00
Andrew Kelley
f75cdd1acd
Merge pull request #8470 from ziglang/stage2-start
stage2: blaze the trail for std lib integration
2021-04-09 10:15:46 -07:00
Andrew Kelley
61b868f9a5 stage2: simplify Decl src_node field
Also fix "previous definition here" error notes to be correct.
2021-04-08 20:37:19 -07:00
Andrew Kelley
9f744f19e7
Merge pull request #8464 from gracefuu/grace/wasm-ops
stage2 wasm: Add division and bitwise/boolean ops &, |, ^, and, or
2021-04-08 13:41:49 -07:00
gracefu
4c71942f84
stage2: Add .div to ir.zig 2021-04-08 05:26:56 +08:00
joachimschmidt557
4ff5a3cd94
stage2 regalloc: Add unit test for getReg 2021-04-07 15:15:14 +02:00
joachimschmidt557
ac2211118f
stage2 regalloc: Add getReg and getRegWithoutTracking 2021-04-06 21:14:00 +02:00
joachimschmidt557
43d364afef stage2 AArch64: Add ldrh and ldrb instructions 2021-04-02 14:46:30 -07:00
joachimschmidt557
228a1ce3e8 stage2 register_manager: Add unit tests for tryAllocReg and allocReg 2021-04-02 12:01:52 -07:00
joachimschmidt557
4efbcad26d stage2 codegen: Extract register management code into separate file 2021-04-02 12:01:52 -07:00
Andrew Kelley
8ebfdc14f6 stage2: implement structs in the frontend
New ZIR instructions:
 * struct_decl_packed
 * struct_decl_extern

New TZIR instruction: struct_field_ptr

Introduce `Module.Struct`. It uses `Value` to store default values and
abi alignments.

Implemented Sema.analyzeStructFieldPtr and zirStructDecl.

Some stuff I changed from `@panic("TODO")` to `log.warn("TODO")`.
It's becoming more clear that we need the lazy value mechanism soon;
Type is becoming unruly, and some of these functions have too much logic
given that they don't have any context for memory management or error
reporting.
2021-04-01 22:39:09 -07:00
Andrew Kelley
070a28e493
Merge pull request #8266 from ziglang/zir-memory-layout
rework ZIR memory layout; overhaul source locations
2021-03-31 23:11:15 -07:00
Andrew Kelley
e272c29c16 Sema: implement switch validation for ranges 2021-03-31 15:06:03 -07:00
joachimschmidt557
1b657e6e41 stage2 codegen: Make sure function return value is in a callee
preserved register
2021-03-31 23:27:50 +02:00
joachimschmidt557
e088a17f56 stage2 AArch64: implement strb and strh 2021-03-31 23:26:49 +02:00
jacob gw
0005b34637 stage2: implement sema for @errorToInt and @intToError 2021-03-28 18:22:01 -07:00
Andrew Kelley
abdbc11c7e stage2: codegen: update asm IR to new names 2021-03-18 22:54:59 -07:00
Andrew Kelley
bd2154da3d stage2: the code is compiling again
(with a lot of things commented out)
2021-03-18 22:48:28 -07:00
Andrew Kelley
b2682237db stage2: get Module and Sema compiling again
There are some `@panic("TODO")` in there but I'm trying to get the
branch to the point where collaborators can jump in.

Next is to repair the seam between LazySrcLoc and codegen's expected
absolute file offsets.
2021-03-18 22:19:28 -07:00
Andrew Kelley
f5aca4a6a1 Merge remote-tracking branch 'origin/master' into zir-memory-layout
I need the enum arrays that were just merged into master.
2021-03-18 15:52:12 -07:00
Andrew Kelley
66245ac834 stage2: Module and Sema are compiling again
Next up is reworking the seam between the LazySrcLoc emitted by Sema
and the byte offsets currently expected by codegen.

And then the big one: updating astgen.zig to use the new memory layout.
2021-03-17 22:54:56 -07:00