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8252 Commits

Author SHA1 Message Date
William Sengir
4e357151a5 stage2: align store for vector-to-array bitcast in LLVM backend 
This was causing a very rare segfault when LLVM would emit `vmovdqa`
using an unaligned memory operand on the stack.
 2022-03-21 16:54:19 -07:00
William Sengir
961248cde3 stage2: make more instructions vector-compatible in LLVM backend 2022-03-21 16:54:19 -07:00
William Sengir
b96699059c stage2: implement cmp_vector for LLVM backend 2022-03-21 16:54:19 -07:00
William Sengir
0f48307041 stage2: add AIR instruction cmp_vector 
The existing `cmp_*` instructions get their result type from `lhs`, but
vector comparison will always return a vector of bools with only the
length derived from its operands. This necessitates the creation of a
new AIR instruction.
 2022-03-21 16:54:19 -07:00
William Sengir
862e63f535 stage2: fix typo in print_air.zig 2022-03-21 16:54:19 -07:00
Jakub Konka
d71bd0300b
Merge pull request #11195 from mparadinha/float-to-int 
stage2: x86_64: implement `@floatToInt` for `f32` and `f64`
 2022-03-21 23:54:36 +01:00
Jakub Konka
a9b6de693c
Merge pull request #11223 from mparadinha/ptr-elem-val 
stage2: x86_64: implement `ptr_elem_val`
 2022-03-21 23:54:17 +01:00
Jakub Konka
00e2113c8b x64: refactor fix reg aliasing in genSetReg 2022-03-21 23:38:01 +01:00
Andrew Kelley
916a65cb7b
Merge pull request #11224 from koachan/sparc64-codegen 
stage2 sparcv9: Add instruction encoder and placeholder codegen impl
 2022-03-21 18:21:31 -04:00
mparadinha
35eaaed7c4 stage2: x86_64: use correct register size when loading things from memory 2022-03-21 19:32:46 +00:00
mparadinha
6d7808e647 stage2: x86_64: implement ptr_elem_val 
The codegen for this is almost identical to `ptr_elem_ptr` except
there's an extra `mov` at the end to replace the pointer with the
value it points to, "in-place" (which can be done in a single
instruction without any extra registers).
 2022-03-21 19:32:46 +00:00
Andrew Kelley
18a43b61f9
Merge pull request #11253 from Vexu/pretty-print-values 
stage2: print values with types
 2022-03-21 15:15:38 -04:00
Veikka Tuominen
0577069af5 stage2 llvm: fix lowerDeclRefValue for function aliases 2022-03-21 15:12:32 -04:00
Veikka Tuominen
a31fe0ff12 stage2: add way to print values with types 2022-03-21 15:03:42 +02:00
Joachim Schmidt
b48d8cce52
Merge pull request #11235 from joachimschmidt557/stage2-riscv 
stage2 RISCV64: remove MCValue.embedded_in_code
 2022-03-21 12:36:47 +01:00
William Sengir
a5dc3f0342 stage2: add safety checks for index out of bounds 2022-03-20 18:04:38 -04:00
Daniel Hooper
911c839e97
add error when binary ops don't have matching whitespace on both sides 
This change also moves the warning about "&&" from the AstGen into the parser so that the "&&" warning can supersede the whitespace warning.
 2022-03-20 12:55:04 +02:00
Andrew Kelley
0576086395 stage2: remove Value.Tag.abi_align_default 
and make Decl alignment & linksection, and struct & union field alignment
be scalar values, not Value values.

YAGNI
 2022-03-20 00:36:44 -07:00
Andrew Kelley
6d73f89bf1 stage2: disable default panic handler when linking -lc 
It's failing to compile std.os.dl_iterate_phdr correctly.
 2022-03-20 00:36:44 -07:00
Daniele Cocca
b6203b89d6 CBE: implement mod, divFloor, divTrunc 2022-03-19 21:01:36 -04:00
Andrew Kelley
1bd595ceea
Merge pull request #11233 from Luukdegram/wasm-tests 
stage2: wasm - union_init and passing tests
 2022-03-19 19:41:55 -04:00
Cody Tapscott
19331b323d stage2: Correctly align decls for comptime allocs 
This updates WipAnonDecl to require an alignment provided by the caller,
which is needed for explicitly aligned comptime allocs.
 2022-03-19 19:41:23 -04:00
Robin Voetter
5c3325588e stage1: make type names more unique 2022-03-19 19:40:46 -04:00
Andrew Kelley
a318aeed9b
Merge pull request #11222 from Vexu/dbg_block 
stage2: add debug info for payload captures + inline function parameters
 2022-03-19 16:05:22 -04:00
Luuk de Gram
56590218c5
wasm: All union/tuple/array tests passing 
This implements improvements/fixes to get all the union, tuple, and array behavior tests passing.
Previously, we lowered parent pointers for field_ptr and element_ptr incompletely. This has now
been improved to recursively lower such pointer.

Also a fix was done to `generateSymbol` when checking a container's layout.
Previously it was assumed to always be a struct. However, the type can also be a tuple, and therefore
panicking. Updating to ask a type's container layout instead allows us to keep a singular branch for both cases.
 2022-03-19 20:56:04 +01:00
Luuk de Gram
2041176c5e
wasm: Implement union_init instruction 
Implements the `@unionInit` builtin instruction.
 2022-03-19 20:56:03 +01:00
Mitchell Hashimoto
6766528657 stage2: fix crash that could happen if as zir fails 
Example scenario:

    test {
        const a: i32 = blk: {
            if (false) break :blk 24;
        };
        _ = a;
    }

Prior to this, this would panic the compiler with a source needed error.
This provides the source as `sema.src`. This is not ideal, since the
line it points to is pretty far from the true issue. (One block out)

But, this prevents the compiler from straight up crashing and follows a
pattern used by similar ZIR which don't provide a src loc.
 2022-03-19 15:55:23 -04:00
joachimschmidt557
a153732d5a
stage2 RISCV64: implement add, sub for registers 2022-03-19 20:44:57 +01:00
joachimschmidt557
7cdc47a4e0
stage2 RISCV64: implement move register to register 2022-03-19 19:48:27 +01:00
Andrew Kelley
69e6d455ce
Merge pull request #11228 from Vexu/panic 
enable default panic handler for stage2 LLVM
 2022-03-19 14:32:09 -04:00
zseri
c6cf40a0c0 fix sigaction double panic 
Fixes #8357
 2022-03-19 19:13:31 +02:00
Veikka Tuominen
12f3c461a4 Sema: implement zirSwitchCaptureElse for error sets 2022-03-19 15:49:27 +02:00
Veikka Tuominen
2757237332 Sema: add error for runtime block peer type being comptime only 2022-03-19 13:36:16 +02:00
joachimschmidt557
956d9f4ce0
stage2 RISCV64: remove MCValue.embedded_in_code 2022-03-19 10:52:59 +01:00
Veikka Tuominen
d56e3c988f stage2: fix inline fn parameter debug info being added to wrong block 2022-03-19 11:40:45 +02:00
Veikka Tuominen
1e1f740347 AstGen: always add dbg_block_end before last instruction 2022-03-19 11:20:38 +02:00
Veikka Tuominen
30e17cd5d0 Sema: add debug info for inline function parameters 2022-03-19 11:20:38 +02:00
Veikka Tuominen
f19731948e Sema: balance dbg_block_begins in case of early return 2022-03-19 11:20:38 +02:00
Veikka Tuominen
739734170e stage2: add debug info for payload captures 2022-03-19 11:20:38 +02:00
Veikka Tuominen
a8520fbd0f stage2: add dbg_block_{begin,end} instruction 2022-03-19 11:20:38 +02:00
Koakuma
731dda18dd stage2 sparcv9: zig fmt 2022-03-19 09:06:58 +07:00
Koakuma
59680b40a1 stage2 sparcv9: Fix unused parameter errors in Codegen 2022-03-19 06:58:50 +07:00
Koakuma
93b16de4b4 stage2 sparcv9: Add placeholder files and generate() function 
Add placeholder files for Codegen, Emit, and Mir stages, complete with
a placeholder implementation of generate() to make it able to be plugged in
to the frontend. At the moment the implementation just panics, it'll be
worked on incrementally later.

Also, this registers the sparcv9 backend files into CMakeLists.txt.
 2022-03-19 06:09:46 +07:00
Andrew Kelley
d5803441cd
Merge pull request #11220 from schmee/vector-bitreverse 
stage2: implement `@bitReverse` for vectors
 2022-03-18 15:27:08 -04:00
Andrew Kelley
e60c0468aa
Merge pull request #11217 from jmc-88/cbe-tuples 
CBE: add support for tuples
 2022-03-18 15:23:40 -04:00
Jakub Konka
338bf55e84
Merge pull request #11216 from joachimschmidt557/stage2-arm 
stage2 ARM: remove MCValue.embedded_in_code
 2022-03-18 20:02:33 +01:00
Mitchell Hashimoto
3865a61a99 stage2: formatting an error_set value should print members, not decl 2022-03-18 14:53:54 -04:00
Andrew Kelley
de8f3bc885 AstGen: remove unused parameter 
This function took a parameter that was only ever used with one value,
obscuring the fact that it was a regular `block` which should be used with
`.break` and not `.break_inline`.
 2022-03-18 11:49:18 -07:00
Mitchell Hashimoto
3e74acb139 AstGen: labeled blocks should always complete with a normal break 
They aren't inline blocks by nature of being labeled.

Fixes #11213
 2022-03-18 11:40:39 -07:00
joachimschmidt557
13321c8070 stage2 regalloc: fix tryAllocRegs for specific situations 
Previously, tryAllocRegs did not take frozen registers into account
when checking if enough registers are available.
 2022-03-18 19:37:01 +01:00