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Merge pull request #11235 from joachimschmidt557/stage2-riscv
stage2 RISCV64: remove MCValue.embedded_in_code
This commit is contained in:
Joachim Schmidt
GitHub
commit
b48d8cce52
@ -111,11 +111,6 @@ const MCValue = union(enum) {
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/// A pointer-sized integer that fits in a register.
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/// If the type is a pointer, this is the pointer address in virtual address space.
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immediate: u64,
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/// The constant was emitted into the code, at this offset.
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/// If the type is a pointer, it means the pointer address is embedded in the code.
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embedded_in_code: usize,
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/// The value is a pointer to a constant which was emitted into the code, at this offset.
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ptr_embedded_in_code: usize,
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/// The value is in a target-specific register.
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register: Register,
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/// The value is in memory at a hard-coded address.
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@ -129,7 +124,7 @@ const MCValue = union(enum) {
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fn isMemory(mcv: MCValue) bool {
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return switch (mcv) {
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.embedded_in_code, .memory, .stack_offset => true,
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.memory, .stack_offset => true,
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else => false,
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};
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}
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@ -148,10 +143,8 @@ const MCValue = union(enum) {
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.dead => unreachable,
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.immediate,
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.embedded_in_code,
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.memory,
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.ptr_stack_offset,
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.ptr_embedded_in_code,
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.undef,
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=> false,
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@ -416,14 +409,17 @@ fn gen(self: *Self) !void {
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});
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// exitlude jumps
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if (self.exitlude_jump_relocs.items.len == 1) {
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// There is only one relocation. Hence,
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// this relocation must be at the end of
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// the code. Therefore, we can just delete
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// the space initially reserved for the
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// jump
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self.mir_instructions.len -= 1;
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} else for (self.exitlude_jump_relocs.items) |jmp_reloc| {
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if (self.exitlude_jump_relocs.items.len > 0 and
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self.exitlude_jump_relocs.items[self.exitlude_jump_relocs.items.len - 1] == self.mir_instructions.len - 2)
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{
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// If the last Mir instruction (apart from the
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// dbg_epilogue_begin) is the last exitlude jump
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// relocation (which would just jump one instruction
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// further), it can be safely removed
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self.mir_instructions.orderedRemove(self.exitlude_jump_relocs.pop());
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}
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for (self.exitlude_jump_relocs.items) |jmp_reloc| {
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_ = jmp_reloc;
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return self.fail("TODO add branches in RISCV64", .{});
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}
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@ -496,10 +492,10 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
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switch (air_tags[inst]) {
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// zig fmt: off
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.add, .ptr_add => try self.airAdd(inst),
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.add, .ptr_add => try self.airBinOp(inst),
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.addwrap => try self.airAddWrap(inst),
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.add_sat => try self.airAddSat(inst),
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.sub, .ptr_sub => try self.airSub(inst),
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.sub, .ptr_sub => try self.airBinOp(inst),
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.subwrap => try self.airSubWrap(inst),
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.sub_sat => try self.airSubSat(inst),
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.mul => try self.airMul(inst),
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@ -927,9 +923,182 @@ fn airSlice(self: *Self, inst: Air.Inst.Index) !void {
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airAdd(self: *Self, inst: Air.Inst.Index) !void {
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/// Don't call this function directly. Use binOp instead.
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///
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/// Calling this function signals an intention to generate a Mir
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/// instruction of the form
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///
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/// op dest, lhs, rhs
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///
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/// Asserts that generating an instruction of that form is possible.
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fn binOpRegister(
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self: *Self,
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tag: Air.Inst.Tag,
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maybe_inst: ?Air.Inst.Index,
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lhs: MCValue,
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rhs: MCValue,
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lhs_ty: Type,
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rhs_ty: Type,
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) !MCValue {
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const lhs_is_register = lhs == .register;
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const rhs_is_register = rhs == .register;
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if (lhs_is_register) self.register_manager.freezeRegs(&.{lhs.register});
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if (rhs_is_register) self.register_manager.freezeRegs(&.{rhs.register});
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const branch = &self.branch_stack.items[self.branch_stack.items.len - 1];
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const lhs_reg = if (lhs_is_register) lhs.register else blk: {
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const track_inst: ?Air.Inst.Index = if (maybe_inst) |inst| inst: {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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break :inst Air.refToIndex(bin_op.lhs).?;
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} else null;
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const reg = try self.register_manager.allocReg(track_inst);
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self.register_manager.freezeRegs(&.{reg});
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if (track_inst) |inst| branch.inst_table.putAssumeCapacity(inst, .{ .register = reg });
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break :blk reg;
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};
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defer self.register_manager.unfreezeRegs(&.{lhs_reg});
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const rhs_reg = if (rhs_is_register) rhs.register else blk: {
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const track_inst: ?Air.Inst.Index = if (maybe_inst) |inst| inst: {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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break :inst Air.refToIndex(bin_op.rhs).?;
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} else null;
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const reg = try self.register_manager.allocReg(track_inst);
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self.register_manager.freezeRegs(&.{reg});
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if (track_inst) |inst| branch.inst_table.putAssumeCapacity(inst, .{ .register = reg });
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break :blk reg;
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};
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defer self.register_manager.unfreezeRegs(&.{rhs_reg});
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const dest_reg = if (maybe_inst) |inst| blk: {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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if (lhs_is_register and self.reuseOperand(inst, bin_op.lhs, 0, lhs)) {
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break :blk lhs_reg;
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} else if (rhs_is_register and self.reuseOperand(inst, bin_op.rhs, 1, rhs)) {
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break :blk rhs_reg;
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} else {
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break :blk try self.register_manager.allocReg(inst);
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}
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} else try self.register_manager.allocReg(null);
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if (!lhs_is_register) try self.genSetReg(lhs_ty, lhs_reg, lhs);
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if (!rhs_is_register) try self.genSetReg(rhs_ty, rhs_reg, rhs);
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const mir_tag: Mir.Inst.Tag = switch (tag) {
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.add => .add,
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.sub => .sub,
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else => unreachable,
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};
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const mir_data: Mir.Inst.Data = switch (tag) {
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.add,
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.sub,
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=> .{ .r_type = .{
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.rd = dest_reg,
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.rs1 = lhs_reg,
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.rs2 = rhs_reg,
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} },
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else => unreachable,
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};
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_ = try self.addInst(.{
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.tag = mir_tag,
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.data = mir_data,
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});
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return MCValue{ .register = dest_reg };
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}
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/// For all your binary operation needs, this function will generate
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/// the corresponding Mir instruction(s). Returns the location of the
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/// result.
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///
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/// If the binary operation itself happens to be an Air instruction,
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/// pass the corresponding index in the inst parameter. That helps
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/// this function do stuff like reusing operands.
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///
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/// This function does not do any lowering to Mir itself, but instead
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/// looks at the lhs and rhs and determines which kind of lowering
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/// would be best suitable and then delegates the lowering to other
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/// functions.
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fn binOp(
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self: *Self,
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tag: Air.Inst.Tag,
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maybe_inst: ?Air.Inst.Index,
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lhs: MCValue,
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rhs: MCValue,
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lhs_ty: Type,
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rhs_ty: Type,
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) InnerError!MCValue {
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switch (tag) {
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// Arithmetic operations on integers and floats
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.add,
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.sub,
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=> {
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO binary operations on floats", .{}),
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.Vector => return self.fail("TODO binary operations on vectors", .{}),
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.Int => {
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assert(lhs_ty.eql(rhs_ty));
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 64) {
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// TODO immediate operands
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return try self.binOpRegister(tag, maybe_inst, lhs, rhs, lhs_ty, rhs_ty);
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} else {
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return self.fail("TODO binary operations on int with bits > 64", .{});
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}
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},
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else => unreachable,
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}
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},
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.ptr_add,
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.ptr_sub,
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=> {
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switch (lhs_ty.zigTypeTag()) {
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.Pointer => {
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const ptr_ty = lhs_ty;
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const elem_ty = switch (ptr_ty.ptrSize()) {
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.One => ptr_ty.childType().childType(), // ptr to array, so get array element type
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else => ptr_ty.childType(),
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};
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const elem_size = elem_ty.abiSize(self.target.*);
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if (elem_size == 1) {
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const base_tag: Air.Inst.Tag = switch (tag) {
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.ptr_add => .add,
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.ptr_sub => .sub,
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else => unreachable,
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};
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return try self.binOpRegister(base_tag, maybe_inst, lhs, rhs, lhs_ty, rhs_ty);
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} else {
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return self.fail("TODO ptr_add with elem_size > 1", .{});
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}
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},
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else => unreachable,
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}
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},
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else => unreachable,
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}
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}
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fn airBinOp(self: *Self, inst: Air.Inst.Index) !void {
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const tag = self.air.instructions.items(.tag)[inst];
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else return self.fail("TODO implement add for {}", .{self.target.cpu.arch});
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const lhs = try self.resolveInst(bin_op.lhs);
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const rhs = try self.resolveInst(bin_op.rhs);
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const lhs_ty = self.air.typeOf(bin_op.lhs);
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const rhs_ty = self.air.typeOf(bin_op.rhs);
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else try self.binOp(tag, inst, lhs, rhs, lhs_ty, rhs_ty);
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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@ -945,12 +1114,6 @@ fn airAddSat(self: *Self, inst: Air.Inst.Index) !void {
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airSub(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else return self.fail("TODO implement sub for {}", .{self.target.cpu.arch});
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airSubWrap(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else return self.fail("TODO implement subwrap for {}", .{self.target.cpu.arch});
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@ -1283,12 +1446,6 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
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.dead => unreachable,
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.immediate => |imm| try self.setRegOrMem(elem_ty, dst_mcv, .{ .memory = imm }),
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.ptr_stack_offset => |off| try self.setRegOrMem(elem_ty, dst_mcv, .{ .stack_offset = off }),
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.ptr_embedded_in_code => |off| {
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try self.setRegOrMem(elem_ty, dst_mcv, .{ .embedded_in_code = off });
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},
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.embedded_in_code => {
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return self.fail("TODO implement loading from MCValue.embedded_in_code", .{});
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},
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.register => {
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return self.fail("TODO implement loading from MCValue.register", .{});
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},
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@ -1331,27 +1488,19 @@ fn airLoad(self: *Self, inst: Air.Inst.Index) !void {
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return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
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}
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fn airStore(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const ptr = try self.resolveInst(bin_op.lhs);
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const value = try self.resolveInst(bin_op.rhs);
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const elem_ty = self.air.typeOf(bin_op.rhs);
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fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type) !void {
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_ = ptr_ty;
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switch (ptr) {
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.none => unreachable,
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.undef => unreachable,
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.unreach => unreachable,
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.dead => unreachable,
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.immediate => |imm| {
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try self.setRegOrMem(elem_ty, .{ .memory = imm }, value);
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try self.setRegOrMem(value_ty, .{ .memory = imm }, value);
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},
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.ptr_stack_offset => |off| {
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try self.genSetStack(elem_ty, off, value);
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},
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.ptr_embedded_in_code => |off| {
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try self.setRegOrMem(elem_ty, .{ .embedded_in_code = off }, value);
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},
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.embedded_in_code => {
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return self.fail("TODO implement storing to MCValue.embedded_in_code", .{});
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try self.genSetStack(value_ty, off, value);
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},
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.register => {
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return self.fail("TODO implement storing to MCValue.register", .{});
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@ -1363,6 +1512,17 @@ fn airStore(self: *Self, inst: Air.Inst.Index) !void {
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return self.fail("TODO implement storing to MCValue.stack_offset", .{});
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},
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}
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}
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fn airStore(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const ptr = try self.resolveInst(bin_op.lhs);
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const value = try self.resolveInst(bin_op.rhs);
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const ptr_ty = self.air.typeOf(bin_op.lhs);
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const value_ty = self.air.typeOf(bin_op.rhs);
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try self.store(ptr, value, ptr_ty, value_ty);
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return self.finishAir(inst, .dead, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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@ -1508,7 +1668,6 @@ fn airCall(self: *Self, inst: Air.Inst.Index, modifier: std.builtin.CallOptions.
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.immediate => unreachable,
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.unreach => unreachable,
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.dead => unreachable,
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.embedded_in_code => unreachable,
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.memory => unreachable,
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.register => |reg| {
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try self.register_manager.getReg(reg, null);
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@ -1520,9 +1679,6 @@ fn airCall(self: *Self, inst: Air.Inst.Index, modifier: std.builtin.CallOptions.
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.ptr_stack_offset => {
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return self.fail("TODO implement calling with MCValue.ptr_stack_offset arg", .{});
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},
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.ptr_embedded_in_code => {
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return self.fail("TODO implement calling with MCValue.ptr_embedded_in_code arg", .{});
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},
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}
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}
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@ -2052,7 +2208,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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switch (mcv) {
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.dead => unreachable,
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.ptr_stack_offset => unreachable,
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.ptr_embedded_in_code => unreachable,
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.unreach, .none => return, // Nothing to do.
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.undef => {
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if (!self.wantSafety())
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@ -2098,6 +2253,20 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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return self.fail("TODO genSetReg 33-64 bit immediates for riscv64", .{}); // glhf
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}
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},
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.register => |src_reg| {
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// If the registers are the same, nothing to do.
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if (src_reg.id() == reg.id())
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return;
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// mov reg, src_reg
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_ = try self.addInst(.{
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.tag = .mv,
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.data = .{ .rr = .{
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.rd = reg,
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.rs = src_reg,
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} },
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});
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},
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.memory => |addr| {
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// The value is in memory at a hard-coded address.
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// If the type is a pointer, it means the pointer address is at this memory location.
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@ -2321,27 +2490,6 @@ fn getResolvedInstValue(self: *Self, inst: Air.Inst.Index) MCValue {
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}
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}
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/// If the MCValue is an immediate, and it does not fit within this type,
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/// we put it in a register.
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/// A potential opportunity for future optimization here would be keeping track
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/// of the fact that the instruction is available both as an immediate
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/// and as a register.
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fn limitImmediateType(self: *Self, operand: Air.Inst.Ref, comptime T: type) !MCValue {
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const mcv = try self.resolveInst(operand);
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const ti = @typeInfo(T).Int;
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switch (mcv) {
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.immediate => |imm| {
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// This immediate is unsigned.
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const U = std.meta.Int(.unsigned, ti.bits - @boolToInt(ti.signedness == .signed));
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if (imm >= math.maxInt(U)) {
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return MCValue{ .register = try self.copyToTmpRegister(Type.initTag(.usize), mcv) };
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}
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},
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else => {},
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}
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return mcv;
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}
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fn lowerDeclRef(self: *Self, tv: TypedValue, decl: *Module.Decl) InnerError!MCValue {
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const ptr_bits = self.target.cpu.arch.ptrBitWidth();
|
||||
const ptr_bytes: u64 = @divExact(ptr_bits, 8);
|
||||
|
||||
@ -43,6 +43,9 @@ pub fn emitMir(
|
||||
for (mir_tags) |tag, index| {
|
||||
const inst = @intCast(u32, index);
|
||||
switch (tag) {
|
||||
.add => try emit.mirRType(inst),
|
||||
.sub => try emit.mirRType(inst),
|
||||
|
||||
.addi => try emit.mirIType(inst),
|
||||
.jalr => try emit.mirIType(inst),
|
||||
.ld => try emit.mirIType(inst),
|
||||
@ -56,6 +59,8 @@ pub fn emitMir(
|
||||
.dbg_prologue_end => try emit.mirDebugPrologueEnd(),
|
||||
.dbg_epilogue_begin => try emit.mirDebugEpilogueBegin(),
|
||||
|
||||
.mv => try emit.mirRR(inst),
|
||||
|
||||
.nop => try emit.mirNop(inst),
|
||||
.ret => try emit.mirNop(inst),
|
||||
|
||||
@ -131,6 +136,17 @@ fn dbgAdvancePCAndLine(self: *Emit, line: u32, column: u32) !void {
|
||||
}
|
||||
}
|
||||
|
||||
fn mirRType(emit: *Emit, inst: Mir.Inst.Index) !void {
|
||||
const tag = emit.mir.instructions.items(.tag)[inst];
|
||||
const r_type = emit.mir.instructions.items(.data)[inst].r_type;
|
||||
|
||||
switch (tag) {
|
||||
.add => try emit.writeInstruction(Instruction.add(r_type.rd, r_type.rs1, r_type.rs2)),
|
||||
.sub => try emit.writeInstruction(Instruction.sub(r_type.rd, r_type.rs1, r_type.rs2)),
|
||||
else => unreachable,
|
||||
}
|
||||
}
|
||||
|
||||
fn mirIType(emit: *Emit, inst: Mir.Inst.Index) !void {
|
||||
const tag = emit.mir.instructions.items(.tag)[inst];
|
||||
const i_type = emit.mir.instructions.items(.data)[inst].i_type;
|
||||
@ -186,6 +202,15 @@ fn mirDebugEpilogueBegin(self: *Emit) !void {
|
||||
}
|
||||
}
|
||||
|
||||
fn mirRR(emit: *Emit, inst: Mir.Inst.Index) !void {
|
||||
const tag = emit.mir.instructions.items(.tag)[inst];
|
||||
const rr = emit.mir.instructions.items(.data)[inst].rr;
|
||||
|
||||
switch (tag) {
|
||||
.mv => try emit.writeInstruction(Instruction.addi(rr.rd, rr.rs, 0)),
|
||||
else => unreachable,
|
||||
}
|
||||
}
|
||||
fn mirUType(emit: *Emit, inst: Mir.Inst.Index) !void {
|
||||
const tag = emit.mir.instructions.items(.tag)[inst];
|
||||
const u_type = emit.mir.instructions.items(.data)[inst].u_type;
|
||||
|
||||
@ -24,6 +24,7 @@ pub const Inst = struct {
|
||||
data: Data,
|
||||
|
||||
pub const Tag = enum(u16) {
|
||||
add,
|
||||
addi,
|
||||
/// Pseudo-instruction: End of prologue
|
||||
dbg_prologue_end,
|
||||
@ -36,9 +37,11 @@ pub const Inst = struct {
|
||||
jalr,
|
||||
ld,
|
||||
lui,
|
||||
mv,
|
||||
nop,
|
||||
ret,
|
||||
sd,
|
||||
sub,
|
||||
};
|
||||
|
||||
/// The position of an MIR instruction within the `Mir` instructions array.
|
||||
@ -68,6 +71,13 @@ pub const Inst = struct {
|
||||
///
|
||||
/// Used by e.g. blr
|
||||
reg: Register,
|
||||
/// Two registers
|
||||
///
|
||||
/// Used by e.g. mv
|
||||
rr: struct {
|
||||
rd: Register,
|
||||
rs: Register,
|
||||
},
|
||||
/// I-Type
|
||||
///
|
||||
/// Used by e.g. jalr
|
||||
@ -76,6 +86,14 @@ pub const Inst = struct {
|
||||
rs1: Register,
|
||||
imm12: i12,
|
||||
},
|
||||
/// R-Type
|
||||
///
|
||||
/// Used by e.g. add
|
||||
r_type: struct {
|
||||
rd: Register,
|
||||
rs1: Register,
|
||||
rs2: Register,
|
||||
},
|
||||
/// U-Type
|
||||
///
|
||||
/// Used by e.g. lui
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user