Merge pull request #11224 from koachan/sparc64-codegen

stage2 sparcv9: Add instruction encoder and placeholder codegen impl

CMakeLists.txt

@@ -614,6 +614,11 @@ set(ZIG_STAGE2_SOURCES
     "${CMAKE_SOURCE_DIR}/src/arch/riscv64/Mir.zig"
     "${CMAKE_SOURCE_DIR}/src/arch/riscv64/bits.zig"
     "${CMAKE_SOURCE_DIR}/src/arch/riscv64/abi.zig"
+    "${CMAKE_SOURCE_DIR}/src/arch/sparcv9/CodeGen.zig"
+    "${CMAKE_SOURCE_DIR}/src/arch/sparcv9/Emit.zig"
+    "${CMAKE_SOURCE_DIR}/src/arch/sparcv9/Mir.zig"
+    "${CMAKE_SOURCE_DIR}/src/arch/sparcv9/bits.zig"
+    "${CMAKE_SOURCE_DIR}/src/arch/sparcv9/abi.zig"
     "${CMAKE_SOURCE_DIR}/src/arch/wasm/CodeGen.zig"
     "${CMAKE_SOURCE_DIR}/src/arch/wasm/Emit.zig"
     "${CMAKE_SOURCE_DIR}/src/arch/wasm/Mir.zig"

src/arch/sparcv9/CodeGen.zig

@@ -0,0 +1,39 @@
+//! SPARCv9 codegen.
+//! This lowers AIR into MIR.
+const std = @import("std");
+const builtin = @import("builtin");
+const link = @import("../../link.zig");
+const Module = @import("../../Module.zig");
+const Air = @import("../../Air.zig");
+const Mir = @import("Mir.zig");
+const Emit = @import("Emit.zig");
+const Liveness = @import("../../Liveness.zig");
+
+const GenerateSymbolError = @import("../../codegen.zig").GenerateSymbolError;
+const FnResult = @import("../../codegen.zig").FnResult;
+const DebugInfoOutput = @import("../../codegen.zig").DebugInfoOutput;
+
+const bits = @import("bits.zig");
+const abi = @import("abi.zig");
+
+const Self = @This();
+
+pub fn generate(
+    bin_file: *link.File,
+    src_loc: Module.SrcLoc,
+    module_fn: *Module.Fn,
+    air: Air,
+    liveness: Liveness,
+    code: *std.ArrayList(u8),
+    debug_output: DebugInfoOutput,
+) GenerateSymbolError!FnResult {
+    _ = bin_file;
+    _ = src_loc;
+    _ = module_fn;
+    _ = air;
+    _ = liveness;
+    _ = code;
+    _ = debug_output;
+
+    @panic("TODO implement SPARCv9 codegen");
+}

src/arch/sparcv9/Emit.zig

@@ -0,0 +1,6 @@
+//! This file contains the functionality for lowering SPARCv9 MIR into
+//! machine code
+
+const Emit = @This();
+const Mir = @import("Mir.zig");
+const bits = @import("bits.zig");

src/arch/sparcv9/Mir.zig

@@ -0,0 +1,11 @@
+//! Machine Intermediate Representation.
+//! This data is produced by SPARCv9 Codegen or SPARCv9 assembly parsing
+//! These instructions have a 1:1 correspondence with machine code instructions
+//! for the target. MIR can be lowered to source-annotated textual assembly code
+//! instructions, or it can be lowered to machine code.
+//! The main purpose of MIR is to postpone the assignment of offsets until Isel,
+//! so that, for example, the smaller encodings of jump instructions can be used.
+
+const Mir = @This();
+const bits = @import("bits.zig");
+const Register = bits.Register;

src/arch/sparcv9/abi.zig

@@ -0,0 +1,12 @@
+const bits = @import("bits.zig");
+const Register = bits.Register;
+
+// Register windowing mechanism will take care of preserving registers
+// so no need to do it manually
+pub const callee_preserved_regs = [_]Register{};
+
+pub const c_abi_int_param_regs_caller_view = [_]Register{ .o0, .o1, .o2, .o3, .o4, .o5 };
+pub const c_abi_int_param_regs_callee_view = [_]Register{ .@"i0", .@"i1", .@"i2", .@"i3", .@"i4", .@"i5" };
+
+pub const c_abi_int_return_regs_caller_view = [_]Register{ .o0, .o1, .o2, .o3, .o4, .o5 };
+pub const c_abi_int_return_regs_callee_view = [_]Register{ .@"i0", .@"i1", .@"i2", .@"i3", .@"i4", .@"i5" };

src/codegen.zig

@@ -108,7 +108,7 @@ pub fn generateFunction(
         //.riscv32 => return Function(.riscv32).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
         .riscv64 => return @import("arch/riscv64/CodeGen.zig").generate(bin_file, src_loc, func, air, liveness, code, debug_output),
         //.sparc => return Function(.sparc).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
-        //.sparcv9 => return Function(.sparcv9).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
+        .sparcv9 => return @import("arch/sparcv9/CodeGen.zig").generate(bin_file, src_loc, func, air, liveness, code, debug_output),
         //.sparcel => return Function(.sparcel).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
         //.s390x => return Function(.s390x).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
         //.tce => return Function(.tce).generate(bin_file, src_loc, func, air, liveness, code, debug_output),