186 Commits

Author SHA1 Message Date
Andrew Kelley
7b8cb881df stage2: improvements towards zig test
* There is now a main_pkg in addition to root_pkg. They are usually the
   same. When using `zig test`, main_pkg is the user's source file and
   root_pkg has the test runner.
 * scanDecl no longer looks for test decls outside the package being
   tested. honoring `--test-filter` is still TODO.
 * test runner main function has a void return value rather than
   `anyerror!void`
 * Sema is improved to generate better AIR for for loops on slices.
 * Sema: fix incorrect capacity calculation in zirBoolBr
 * Sema: add compile errors for trying to use slice fields as an lvalue.
 * Sema: fix type coercion for error unions
 * Sema: fix analyzeVarRef generating garbage AIR
 * C codegen: fix renderValue for error unions with 0 bit payload
 * C codegen: implement function pointer calls
 * CLI: fix usage text

 Adds 4 new AIR instructions:

  * slice_len, slice_ptr: to get the ptr and len fields of a slice.
  * slice_elem_val, ptr_slice_elem_val: to get the element value of
    a slice, and a pointer to a slice.

AstGen gains a new functionality:

 * One of the unused flags of struct decls is now used to indicate
   structs that are known to have non-zero size based on the AST alone.
2021-07-23 22:42:31 -07:00
Jakub Konka
def1359187 Merge remote-tracking branch 'origin/master' into zld-incremental-2 2021-07-22 09:34:44 +02:00
Jakub Konka
e05b1e0e07 macho: fix reloc generation for stubs and GOT entries
The current approach is somewhat hacky, however, works well for
one-off self-hosted linking.
2021-07-21 23:05:03 +02:00
Jakub Konka
845c906e6a macho: add relocations for GOT cells
in self-hosted compiler.
2021-07-21 17:58:05 +02:00
Andrew Kelley
bf09dd87b6 codegen: fix lowering of AIR br instruction
It incorrectly did not process the death of its operand.
2021-07-20 19:30:30 -07:00
Andrew Kelley
1097b0ec77 codegen: fix lowering of AIR return instruction
It incorrectly did not process the death of its operand. Additionally:

 * delete dead code accidentally introduced in fe14e339458a578657f3890f00d654a15c84422c
 * improve AIR printing code to include liveness data for operands.
   Now an exclamation point ("!") indicates the tombstone of an AIR
   instruction.
2021-07-20 18:51:40 -07:00
Lewis Gaul
bf8e347b1b Get codegen.zig to compile - use '{d}' format for Air.Inst.Index values 2021-07-20 12:19:16 -07:00
Andrew Kelley
4a0f38bb76 stage2: update LLVM backend to new AIR memory layout
Also fix compile errors when not using -Dskip-non-native
2021-07-20 12:19:16 -07:00
Andrew Kelley
d17f492017 stage2: miscellaneous fixes for the branch
* Breaking language change: inline assembly must use string literal
   syntax. This is in preparation for inline assembly improvements that
   involve more integration with the Zig language. This means we cannot
   rely on text substitution.
 * Liveness: properly handle inline assembly and function calls with
   more than 3 operands.
   - More than 35 operands is not yet supported. This is a low priority
     to implement.
   - This required implementation in codegen.zig as well.
 * Liveness: fix bug causing incorrect tomb bits.
 * Sema: enable switch expressions that are evaluated at compile-time.
   - Runtime switch instructions still need to be reworked in this
     branch. There was a TODO left here (by me) with a suggestion to do
     some bigger changes as part of the AIR memory reworking. Now that
     time has come and I plan to honor the suggestion in a future commit
     before merging this branch.
 * AIR printing: fix missing ')' on alive instructions.

We're back to "hello world" working for the x86_64 backend.
2021-07-20 12:19:16 -07:00
Andrew Kelley
8082660118 stage2: codegen.zig updated to new AIR memory layout 2021-07-20 12:19:16 -07:00
Jacob G-W
3a41e4430e codegen: add FnResult type which is a Result that removes externally_managed 2021-07-20 12:19:16 -07:00
Andrew Kelley
c09b973ec2 stage2: compile error fixes for AIR memory layout branch
Now the branch is compiling again, provided that one uses
`-Dskip-non-native`, but many code paths are disabled. The code paths
can now be re-enabled one at a time and updated to conform to the new
AIR memory layout.
2021-07-20 12:19:16 -07:00
Andrew Kelley
0f38f68696 stage2: Air and Liveness are passed ephemerally
to the link infrastructure, instead of being stored with Module.Fn. This
moves towards a strategy to make more efficient use of memory by not
storing Air or Liveness data in the Fn struct, but computing it on
demand, immediately sending it to the backend, and then immediately
freeing it.

Backends which want to defer codegen until flush() such as SPIR-V
must move the Air/Liveness data upon `updateFunc` being called and keep
track of that data in the backend implementation itself.
2021-07-20 12:19:16 -07:00
Andrew Kelley
913393fd3b stage2: first pass over Module.zig for AIR memory layout 2021-07-20 12:19:16 -07:00
Andrew Kelley
ee6432537e stage2: first pass over codegen.zig for AIR memory layout 2021-07-20 12:19:16 -07:00
Andrew Kelley
3c3abaf390 stage2: update liveness analysis to new AIR memory layout
It's pretty compact, with each AIR instruction only taking up 4 bits,
plus a sparse table for special instructions such as conditional branch,
switch branch, and function calls with more than 2 arguments.
2021-07-20 12:18:14 -07:00
Andrew Kelley
5d6f7b44c1 stage2: rework AIR memory layout
This commit changes the AIR file and the documentation of the memory
layout. The actual work of modifying the surrounding code (in Sema and
codegen) is not yet done.
2021-07-20 12:18:14 -07:00
Jakub Konka
a442b165f1 macho: add stub relocs when adding extern fn
in self-hosted.
2021-07-20 20:33:07 +02:00
Jakub Konka
2828cd2983 zld: migrate symbol mgmt to incremental backend 2021-07-18 15:05:52 +02:00
Jacob G-W
968d1ecf17 stage2 plan9: add aarch64 support 2021-07-11 01:58:26 -04:00
Andrew Kelley
476faef97a plan9 cleanups
* rename files to adhere to conventions
 * remove unnecessary function / optionality
 * fix merge conflict
 * better panic message
 * remove unnecessary TODO comment
 * proper namespacing of declarations
 * clean up documentation comments
 * no copyright header needed for a brand new zig file that is not
   copied from anywhere
2021-07-08 14:24:16 -07:00
Jacob G-W
4eb778fc3e plan9 linker: remove unused stuff 2021-07-08 14:12:08 -07:00
Jacob G-W
1c2facaf6b stage2: include enough inline asm support for more plan9 syscalls
Also make the exit more correct by exiting 0 rather than random
stuff on the stack.
2021-07-08 14:12:08 -07:00
Jacob G-W
db2d5b49c6 plan9 linker: use a global offset table
this simplifies stuff and makes us not have to use relocations
2021-07-08 14:12:07 -07:00
Jacob G-W
3e59c15025 plan9 linker: do relocations 2021-07-08 14:10:49 -07:00
Jacob G-W
798162e509 plan9 linker: make runnable binaries
We can now run binaries! (they segfault, but still run!)
2021-07-08 14:10:49 -07:00
Andrew Kelley
5c8bd443d9 stage2: fix if expressions on error unions
AstGen had the then-else logic backwards for if expressions
on error unions. This commit fixes it.

Turns out AstGen only really needs `is_non_null` and `is_non_err`,
and does not need the `is_null` or `is_err` variants. So I removed the
`is_null{,_ptr}` and `is_err{,_ptr}` ZIR instructions (-4) and
added `is_non_err`, `is_non_err_ptr` ZIR instructions (+2) for
a total of (-2) ZIR instructions, giving us a tiny bit more headroom
within the 256 tag limit. This required swapping the order of
then/else blocks in a handful of cases, but ultimately means the
ZIR will be in the same as source order, which is convenient
when debugging.

AIR code on the other hand, gains the `is_non_err` and `is_non_err_ptr`
instructions.

Sema: fix logic in zirErrUnionCode and zirErrUnionCodePtr returning the
wrong result type.
2021-07-07 19:50:56 -07:00
Andrew Kelley
5816997ae7 stage2: get tests passing
* implement enough of ret_err_value to pass wasm tests
 * only do the proper `@panic` implementation for the backends which
   support it, which is currently only the C backend. The other backends
   will see `@breakpoint(); unreachable;` same as before.
   - I plan to do AIR memory layout reworking as a prerequisite to
     fixing other backends, because that will help me put all the
     constants up front, which will allow the codegen to lower to memory
     without jumps.
 * `@panic` is implemented using anon decls for the message. Makes it
   easier on the backends. Might want to look into re-using decls for
   this in the future.
 * implement DWARF .debug_info for pointer-like optionals.
2021-07-07 14:17:04 -07:00
Andrew Kelley
06412e04f9 cleanups related to unused params 2021-06-21 17:03:04 -07:00
Jacob G-W
9fffffb07b fix code broken from previous commit 2021-06-21 17:03:03 -07:00
Jacob G-W
641ecc260f std, src, doc, test: remove unused variables 2021-06-21 17:03:03 -07:00
g-w1
e13a182990
stage2 Sema: implement @intToPtr (#9144)
Co-authored-by: Veikka Tuominen <git@vexu.eu>
2021-06-21 18:47:34 +03:00
Jacob G-W
a95fdb0635 stage2: simplify codegen for errorToInt and intToError
We can just use bitcast instead of error_to_int, int_to_error since
errorToInt and intToError do not actually do anything, just change types.
This allows us to remove 2 air ops that were the exact same as bitcast
2021-06-21 18:45:28 +03:00
joachimschmidt557
96c60bcca5 stage2 codegen: Remove hacks for discontinued SPU II backend 2021-06-09 21:37:23 +03:00
Martin Wickham
fc9430f567 Breaking hash map changes for 0.8.0
- hash/eql functions moved into a Context object
- *Context functions pass an explicit context
- *Adapted functions pass specialized keys and contexts
- new getPtr() function returns a pointer to value
- remove functions renamed to fetchRemove
- new remove functions return bool
- removeAssertDiscard deleted, use assert(remove(...)) instead
- Keys and values are stored in separate arrays
- Entry is now {*K, *V}, the new KV is {K, V}
- BufSet/BufMap functions renamed to match other set/map types
- fixed iterating-while-modifying bug in src/link/C.zig
2021-06-03 17:02:16 -05:00
joachimschmidt557
e8236551ab stage2: Move BlockData out of ir.Inst.Block 2021-05-22 21:15:25 -04:00
Andrew Kelley
79dee75b1c stage2: rename ir.zig to air.zig
We've settled on the nomenclature for the artifacts the compiler
pipeline produces:

1. Tokens
2. AST (Abstract Syntax Tree)
3. ZIR (Zig Intermediate Representation)
4. AIR (Analyzed Intermediate Representation)
5. Machine Code

Renaming `ir` identifiers to `air` will come with the inevitable
air-memory-layout branch that I plan to start after the 0.8.0 release.
2021-05-22 14:29:16 -07:00
Andrew Kelley
615d45da77 Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgen
Conflicts:
 * src/codegen/spirv.zig
 * src/link/SpirV.zig

We're going to want to improve the stage2 test harness to print
the source file name when a compile error occurs otherwise std lib
contributors are going to see some confusing CI failures when they cause
stage2 AstGen compile errors.
2021-05-17 19:30:38 -07:00
joachimschmidt557
65cee0b3fd stage2 ARM: correct spilling in genArmMul as well 2021-05-17 17:18:01 -04:00
Andrew Kelley
597082adf4 Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgen
Conflicts:
 * build.zig
 * src/Compilation.zig
 * src/codegen/spirv/spec.zig
 * src/link/SpirV.zig
 * test/stage2/darwin.zig
   - this one might be problematic; start.zig looks for `main` in the
     root source file, not `_main`. Not sure why there is an underscore
     there in master branch.
2021-05-15 21:44:38 -07:00
Andrew Kelley
07606d12da stage2: remove SPU Mark II backend
As it stands, the backend is incomplete, and there is no active contributor,
making it dead weight.

However, anyone is free to resurrect this backend at any time.
2021-05-15 21:25:42 -07:00
Andrew Kelley
dc036f5b6f codegen: implement const value rendering for ints <= 64 bits 2021-05-15 21:00:15 -07:00
joachimschmidt557
8b4e91e18c stage2 register manager: clean up API and add more unit tests 2021-05-14 15:12:33 -04:00
Andrew Kelley
c9cc09a3bf Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgen
Conflicts:
 * lib/std/os/linux.zig
 * lib/std/os/windows/bits.zig
 * src/Module.zig
 * src/Sema.zig
 * test/stage2/test.zig

Mainly I wanted Jakub's new macOS code for respecting stack size, since
we now depend on it for debug builds able to pass one of the test cases
for recursive comptime function calls with `@setEvalBranchQuota`.

The conflicts were all trivial.
2021-05-12 16:41:20 -07:00
joachimschmidt557
d211dc37c8 stage2 ARM: Overhaul of genArmBinOp 2021-05-09 08:48:58 +02:00
Andrew Kelley
b88d381dec
Merge pull request #8474 from gracefuu/grace/encode-instruction
stage2 x86_64: encoding helpers, fix bugs
2021-05-09 01:36:51 -04:00
Andrew Kelley
eadcefc124 stage2: dbg_stmt ZIR instructions have line/col
instead of node indexes.

 * AstGen: dbg_stmt instructions now have line and column indexes,
   relative to the parent declaration. This allows codegen to emit debug
   info without having the source bytes, tokens, or AST nodes loaded
   in memory.
 * ZIR: each decl has the absolute line number. This allows computing
   line numbers from offsets without consulting source code bytes.

Memory management: creating a function definition does not prematurely
set the Decl arena. Instead the function is allocated with the general
purpose allocator.

Codegen no longer looks at source code bytes for any reason. They can
remain unloaded from disk.
2021-05-01 21:57:52 -07:00
Andrew Kelley
0c71d2fdc1 stage2: implement semantic analysis for functions and global vars
* AstGen: add missing `break_inline` for comptime blocks.
 * Module: call getTree() in byteOffset(). This generates the AST when
   using cached ZIR and compile errors need to be reported.
 * Scope.File: distinguish between successful ZIR generation and AIR
   generation (when Decls in scope have been scanned).
   - `semaFile` correctly avoids doing work twice.
 * Implement first pass at `lookupInNamespace`. It has various TODOs
   left, such as `usingnamespace`, and setting up Decl dependencies.
2021-04-28 22:43:26 -07:00
Andrew Kelley
f86469bc5e stage2: semaDecl properly analyzes the decl block
Also flattened out Decl TypedValue fields into
ty, val, has_tv
and add relevant fields to Decl for alignment and link section.
2021-04-28 16:57:01 -07:00
Andrew Kelley
df24ce52b1 Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgen
In particular I wanted to take advantage of the new hex float parsing
code.
2021-04-28 14:57:38 -07:00