543 Commits

Author SHA1 Message Date
Koakuma
18c98eb429 stage2: sparcv9: Placeholder for Air instructions in genBody 2022-04-14 22:18:06 +07:00
Koakuma
94d70bdb69 stage2: sparcv9: Change ordering in Mir Tag 2022-04-14 22:18:05 +07:00
Koakuma
94a84e783e stage2: sparcv9: Implement basic prologue/epilogue Mir emission 2022-04-14 22:18:05 +07:00
Koakuma
927706e6d0 stage2: sparcv9: Emit debug inst placeholder 2022-04-14 22:18:05 +07:00
Koakuma
cf13356dab stage2: sparcv9: Mir extraData implementation 2022-04-14 22:18:05 +07:00
Koakuma
1ba5227216 stage2: sparcv9: Initial resolveCallingConventionValues implementation 2022-04-14 22:18:05 +07:00
Koakuma
a5a89fde13 stage2: sparcv9: Add skeleton codegen impl and necessary fields 2022-04-14 22:18:05 +07:00
Koakuma
a30688ef2a stage2: sparcv9: Add some initial checks in codegen 2022-04-14 22:18:05 +07:00
Jakub Konka
edb428fae4 macho,x64: resolve debug info relocs for RIP-based addressing
Sometimes we will want to generate debug info for a constant that
has been lowered to memory and not copied anywhere else. For this
we will need to defer resolution on PIE platforms until all locals
(including GOT entries) have been allocated.
2022-04-13 19:50:23 +02:00
Jakub Konka
3f912430bd stage2,x64: deref memory if referenced via GOT for local vars 2022-04-13 16:24:56 +02:00
Jakub Konka
4c50a27d68 stage2,x64: generate debug info for local vars at hardcoded mem addr 2022-04-13 14:31:04 +02:00
Jakub Konka
baeff1762b stage2,x64: recursively mark decls as alive when lowering 2022-04-13 13:52:01 +02:00
Andrew Kelley
b0edd8752a Liveness: modify encoding to support over 32 operands
Prior to this, Liveness encoded `asm`, `call`, and `aggregate_init` with
a single 32-bit integer, allowing up to 35 operands (3 are provided by
the regular tomb_bits). However, the Zig language allows function calls
with more than 35 arguments, inline assembly with more than 35 inputs,
and anonymous tuples with more than 35 elements.

The new encoding stores an index to the extra array instead of the bits
directly, and then as many extra elements as needed to encode all the
operands. The MSB is used as a flag to tell which element is the last
one, allowing for 31 bits per element.

Prior to this, print_air did not bother correctly printing tombstones
for these instructions; now it does.

In addition to updating the BigTomb iteration logic in the machine code
backends, this commit extracts the common logic into the Liveness namespace.
2022-04-12 11:22:12 -07:00
Andrew Kelley
6ae8fe193b Liveness: utilize Air.refToIndex 2022-04-07 23:19:19 -07:00
Luuk de Gram
ac873367b9 wasm: Use 'select' instruction for max/min
Rather than using blocks and control flow to check which operand is the maximum or minimum,
we use wasm's `select` instruction which returns us the operand based on a result from a comparison.
This saves us the need of control flow, as well as reduce the instruction count from 13 to 7.
2022-04-05 21:56:25 +02:00
Damien Firmenich
5fafcc2b62
zig fmt: remove trailing whitespace on doc comments
Fixes #11353

The renderer treats comments and doc comments differently since doc
comments are parsed into the Ast. This commit adds a check after getting
the text for the doc comment and trims whitespace at the end before
rendering.

The `a = 0,` in the test is here to avoid a ParseError while parsing the
test.
2022-04-05 18:08:33 +03:00
Jakub Konka
364e53f3bf dwarf: emit debug info for local variables on x86_64
Add support for emitting debug info for local variables within a subprogram.
This required moving bits responsible for populating the debug info back to
`CodeGen` from `Emit` as we require the operand to be resolved at callsite
plus we need to know its type. Without enforcing this, we could end up
with a `dead` mcv.
2022-04-04 21:46:53 +02:00
Luuk de Gram
2c40b37f79 wasm: Implement @ctz for bitsize <= 64
Implements the `ctz` AIR instruction for integers with bitsize <= 64.
When the bitsize of the integer does not match the bitsize of a wasm type,
we first XOR the value with the value of (1<<bitsize) to set the right bits
and ensure we will only count the trailing zeroes of the integer with the correct bitsize.
2022-04-02 21:54:01 +02:00
Luuk de Gram
bd27fe2bf5 wasm: Implement @clz
Implements the `clz` AIR instruction for integers with bitsize <= 64.
When the bitsize of the integer is not the same as wasm's bitsize,
we substract the difference in bits as those will always be 0 for the integer, but should
not be counted towards the end result. We also wrap the result to ensure it fits
in the result type as documented in the language reference.
2022-04-02 21:54:01 +02:00
Luuk de Gram
5ba03369ee wasm: Implement @mulAdd for f32, f64
This implements the `mul_add` AIR instruction for floats of bitsize 32 and 64.
f16's will require us being able to extend and truncate f16's to correctly
store and load them without losing the accuracy.
2022-04-02 21:54:01 +02:00
Luuk de Gram
219fa192c6 wasm: Implement @maximum & @minimum
This implements the `max` and `min` AIR instructions by checking
whether LHS is great/lesser than RHS. If that's the case, we assign
LHS to the result, otherwise assign RHS to it instead.
2022-04-02 21:54:01 +02:00
joachimschmidt557
8c12ad98b8
stage2 ARM: implement mul_with_overflow for ints <= 32 bits 2022-04-01 22:51:18 +02:00
joachimschmidt557
c4778fc029
stage2 ARM: implement mul_with_overflow for ints <= 16 bits 2022-04-01 22:02:56 +02:00
joachimschmidt557
77e70189f4
stage2 ARM: implement shl_with_overflow for ints <= 32 bits 2022-04-01 22:02:56 +02:00
joachimschmidt557
37a8c28802
stage2 ARM: implement add/sub_with_overflow for ints < 32 bits 2022-04-01 22:02:56 +02:00
joachimschmidt557
7285f0557c
stage2 ARM: implement add/sub_with_overflow for u32/i32 2022-04-01 22:02:55 +02:00
joachimschmidt557
e2e69803dc
stage2 ARM: change binOp lowering mechanism to use Mir tags
The Air -> Mir correspondence is not 1:1, so this better represents
what Mir insruction we actually want to generate.
2022-04-01 22:02:51 +02:00
Jakub Konka
fd29ddc06c x64: implement add/sub with wrapping and xor op 2022-04-01 11:37:18 +02:00
Veikka Tuominen
75c2cff40e stage2: handle assembly input names 2022-03-31 01:33:28 -04:00
Jakub Konka
f5d9160f1b dwarf: pass DeclState around instead of storing a temp global in Dwarf
Avoids many pitfalls connected with premature/early return in case
there are errors with Decl, etc. This is effectively bringing back
the old design however in a much nicer packaging, where every
mechanism related to tracking Decl's debug info is now nicely
wrapped in a single struct (aka the `DeclState`). This includes
relocation table, type arena, etc. It is now the caller's
responsibility to deinit the state (so that no memory is leaked)
after `Decl` has been analysed (or errored out). The caller here
is typically a linker such as `Elf` or `MachO`.
2022-03-30 14:21:13 -04:00
Jakub Konka
b153e156b1
Merge pull request #11342 from ziglang/stage2-x64-mul-div
x64: use all available registers (caller and callee), and fix how we multiply (fixes @mulWithOverflow for byte-size operands)
2022-03-30 11:22:35 +02:00
Andrew Kelley
c21f046a8b Sema: enhance is_non_err to be comptime more often
* Sema: store the precomputed monomorphed_funcs hash inside Module.Fn.
   This is important because it may be accessed when resizing monomorphed_funcs
   while this Fn has already been added to the set, but does not have the
   owner_decl, comptime_args, or other fields populated yet.
 * Sema: in `analyzeIsNonErr`, take advantage of the AIR tag being
   `wrap_errunion_payload` to infer that `is_non_err` is comptime true
   without performing any error set resolution.
   - Also add some code to check for empty inferred error sets in this
     function. If necessary we do resolve the inferred error set.
 * Sema: queue full type resolution of payload type when
   `wrap_errunion_payload` AIR instruction is emitted. This ensures the
   backend may check the alignment of it.
 * Sema: resolveTypeFully now additionally resolves comptime-only
   status.

closes #11306
2022-03-30 00:47:55 -07:00
Andrew Kelley
05947ea870 stage2: implement @intToError with safety
This commit introduces a new AIR instruction `cmp_lt_errors_len`. It's
specific to this use case for two reasons:

 * The total number of errors is not stable during semantic analysis; it
   can only be reliably checked when flush() is called. So the backend
   that is lowering the instruction must emit a relocation of some kind
   and then populate it during flush().
 * The fewer AIR instructions in memory, the better for compiler
   performance, so we squish complex meanings into AIR tags without
   hesitation.

The instruction is implemented only in the LLVM backend so far. It does
this by creating a simple function which is gutted and re-populated
with each flush().

AstGen now uses ResultLoc.coerced_ty for `@intToError` and Sema does the
coercion.
2022-03-29 22:19:06 -07:00
Jakub Konka
376d0878ec x64: spill .rdi to stack if expecting return value saved on stack
Since .rdi is not part of the callee saved registers, it needs to be
proactively spilled to the stack so that we don't clobber the
return address where to save the return value.
2022-03-30 00:37:42 +02:00
Jakub Konka
d447cd940d x64: track callee and caller saved registers
This is now required to correctly track and spill registers
required for some ops such `mul` or `div` (both required use of
`.rax` and `.rdx` registers).
2022-03-30 00:37:42 +02:00
Jakub Konka
60879bc8ae x64: clean up instruction tracking for div/mul ops 2022-03-30 00:37:42 +02:00
Jakub Konka
ee6e3aef5d x64: redo @mulWithOverflow using rax/rdx based multiplication 2022-03-30 00:37:42 +02:00
Jakub Konka
f9773ab622 x64: clean up abstraction for generating integer division 2022-03-30 00:37:42 +02:00
Jakub Konka
e6729036e4 x64: partially fix genImul, enable overflow tests 2022-03-28 17:45:50 +02:00
Jakub Konka
107052aded x64: implement add, sub and mul with overflow 2022-03-28 16:37:35 +02:00
Jakub Konka
b8cd56dc94
Merge pull request #11300 from ziglang/stage2-debug-error-sets 2022-03-28 07:40:33 +02:00
Jakub Konka
366ec21052 dwarf: track type relocation state in Dwarf module 2022-03-27 20:53:06 +02:00
Luuk de Gram
3114faddd8
wasm: Implement overflow arithmetic
This implements the overflow arithmetic for unsigned and signed integers.
Meaning the following instructions:
- @addWithOverflow
- @subWithOverflow
- @shlWithOverflow
- @mulWithOverflow
2022-03-27 19:00:49 +02:00
Luuk de Gram
97448e4d5f wasm: Only generate import when referenced
Rather than creating an import for externs on updateDecl, we now
generate them when they're referenced. This is required so using @TypeOf(extern_fn())
will not emit the import into the binary (causing an incorrect function type index
as it won't be fully analyzed).
2022-03-26 21:20:29 +01:00
Andrew Kelley
88e98a0611
Merge pull request #11289 from schmee/stage2-select
stage2: implement `@select`
2022-03-26 00:33:22 -04:00
Andrew Kelley
bcd7eb012a
Merge pull request #11304 from joachimschmidt557/stage2-aarch64
stage2 AArch64: remove MCValue.embedded_in_code
2022-03-25 22:22:47 -04:00
joachimschmidt557
c1098e9036 stage2 x86_64: remove MCValue.embedded_in_code 2022-03-25 22:22:16 -04:00
joachimschmidt557
f7da4b9bc8
stage2 AArch64: change semantics of MCValue.stack_offset
Mirrors the changes performed to stack_offset in the ARM backend
2022-03-25 19:21:34 +01:00
joachimschmidt557
16e4966332
stage2 AArch64: remove MCValue.embedded_in_code 2022-03-25 19:21:34 +01:00
joachimschmidt557
061d6699c0
stage2 AArch64: lower cmp to binOp 2022-03-25 19:21:34 +01:00