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stage2 AArch64: lower cmp to binOp

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joachimschmidt557 2022-03-17 22:58:33 +01:00
parent 1c33ea2c35
commit 061d6699c0
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4 changed files with 111 additions and 127 deletions
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179
src/arch/aarch64/CodeGen.zig
View File

@ -1058,7 +1058,7 @@ fn airNot(self: *Self, inst: Air.Inst.Index) !void {
_ = try self.addInst(.{
.tag = .mvn,
.data = .{ .rr_imm6_shift = .{
.data = .{ .rr_imm6_logical_shift = .{
.rd = dest_reg,
.rm = op_reg,
.imm6 = 0,
@ -1188,6 +1188,7 @@ fn binOpRegister(
.sub,
.ptr_sub,
=> .sub_shifted_register,
.cmp_eq => .cmp_shifted_register,
.mul => .mul,
.bit_and,
.bool_and,
@ -1219,6 +1220,12 @@ fn binOpRegister(
.imm6 = 0,
.shift = .lsl,
} },
.cmp_eq => .{ .rr_imm6_shift = .{
.rn = lhs_reg,
.rm = rhs_reg,
.imm6 = 0,
.shift = .lsl,
} },
.mul,
.shl,
.shl_exact,
@ -1296,20 +1303,23 @@ fn binOpImmediate(
};
defer self.register_manager.unfreezeRegs(&.{lhs_reg});
const dest_reg = if (maybe_inst) |inst| blk: {
const bin_op = self.air.instructions.items(.data)[inst].bin_op;
const dest_reg = switch (tag) {
.cmp_eq => undefined, // cmp has no destination register
else => if (maybe_inst) |inst| blk: {
const bin_op = self.air.instructions.items(.data)[inst].bin_op;
if (lhs_is_register and self.reuseOperand(
inst,
if (lhs_and_rhs_swapped) bin_op.rhs else bin_op.lhs,
if (lhs_and_rhs_swapped) 1 else 0,
lhs,
)) {
break :blk lhs_reg;
} else {
break :blk try self.register_manager.allocReg(inst);
}
} else try self.register_manager.allocReg(null);
if (lhs_is_register and self.reuseOperand(
inst,
if (lhs_and_rhs_swapped) bin_op.rhs else bin_op.lhs,
if (lhs_and_rhs_swapped) 1 else 0,
lhs,
)) {
break :blk lhs_reg;
} else {
break :blk try self.register_manager.allocReg(inst);
}
} else try self.register_manager.allocReg(null),
};
if (!lhs_is_register) try self.genSetReg(lhs_ty, lhs_reg, lhs);
@ -1325,6 +1335,7 @@ fn binOpImmediate(
.signed => Mir.Inst.Tag.asr_immediate,
.unsigned => Mir.Inst.Tag.lsr_immediate,
},
.cmp_eq => .cmp_immediate,
else => unreachable,
};
const mir_data: Mir.Inst.Data = switch (tag) {
@ -1344,6 +1355,10 @@ fn binOpImmediate(
.rn = lhs_reg,
.shift = @intCast(u6, rhs.immediate),
} },
.cmp_eq => .{ .r_imm12_sh = .{
.rn = lhs_reg,
.imm12 = @intCast(u12, rhs.immediate),
} },
else => unreachable,
};
@ -1381,6 +1396,7 @@ fn binOp(
// Arithmetic operations on integers and floats
.add,
.sub,
.cmp_eq,
=> {
switch (lhs_ty.zigTypeTag()) {
.Float => return self.fail("TODO binary operations on floats", .{}),
@ -1394,12 +1410,13 @@ fn binOp(
// operands
const lhs_immediate_ok = switch (tag) {
.add => lhs == .immediate and lhs.immediate <= std.math.maxInt(u12),
.sub => false,
.sub, .cmp_eq => false,
else => unreachable,
};
const rhs_immediate_ok = switch (tag) {
.add,
.sub,
.cmp_eq,
=> rhs == .immediate and rhs.immediate <= std.math.maxInt(u12),
else => unreachable,
};
@ -2036,8 +2053,7 @@ fn genInlineMemcpy(
// cmp count, len
_ = try self.addInst(.{
.tag = .cmp_shifted_register,
.data = .{ .rrr_imm6_shift = .{
.rd = .xzr,
.data = .{ .rr_imm6_shift = .{
.rn = count,
.rm = len,
.imm6 = 0,
@ -2615,107 +2631,44 @@ fn airRetLoad(self: *Self, inst: Air.Inst.Index) !void {
fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
const bin_op = self.air.instructions.items(.data)[inst].bin_op;
const result: MCValue = if (self.liveness.isUnused(inst)) .dead else result: {
const lhs = try self.resolveInst(bin_op.lhs);
const rhs = try self.resolveInst(bin_op.rhs);
const lhs_ty = self.air.typeOf(bin_op.lhs);
if (self.liveness.isUnused(inst))
return self.finishAir(inst, .dead, .{ bin_op.lhs, bin_op.rhs, .none });
var int_buffer: Type.Payload.Bits = undefined;
const int_ty = switch (lhs_ty.zigTypeTag()) {
.Vector => return self.fail("TODO AArch64 cmp vectors", .{}),
.Enum => lhs_ty.intTagType(&int_buffer),
.Int => lhs_ty,
.Bool => Type.initTag(.u1),
.Pointer => Type.usize,
.ErrorSet => Type.initTag(.u16),
.Optional => blk: {
if (lhs_ty.isPtrLikeOptional()) {
break :blk Type.usize;
}
const ty = self.air.typeOf(bin_op.lhs);
if (ty.abiSize(self.target.*) > 8) {
return self.fail("TODO cmp for types with size > 8", .{});
}
try self.spillCompareFlagsIfOccupied();
self.compare_flags_inst = inst;
const signedness: std.builtin.Signedness = blk: {
// by default we tell the operand type is unsigned (i.e. bools and enum values)
if (ty.zigTypeTag() != .Int) break :blk .unsigned;
// incase of an actual integer, we emit the correct signedness
break :blk ty.intInfo(self.target.*).signedness;
};
const lhs = try self.resolveInst(bin_op.lhs);
const rhs = try self.resolveInst(bin_op.rhs);
const result: MCValue = result: {
const lhs_is_register = lhs == .register;
const rhs_is_register = rhs == .register;
// lhs should always be a register
const rhs_should_be_register = switch (rhs) {
.immediate => |imm| imm < 0 or imm > std.math.maxInt(u12),
else => true,
};
if (lhs_is_register) self.register_manager.freezeRegs(&.{lhs.register});
defer if (lhs_is_register) self.register_manager.unfreezeRegs(&.{lhs.register});
if (rhs_is_register) self.register_manager.freezeRegs(&.{rhs.register});
defer if (rhs_is_register) self.register_manager.unfreezeRegs(&.{rhs.register});
var lhs_mcv = lhs;
var rhs_mcv = rhs;
// Allocate registers
if (rhs_should_be_register) {
if (!lhs_is_register and !rhs_is_register) {
const regs = try self.register_manager.allocRegs(2, .{
Air.refToIndex(bin_op.lhs).?, Air.refToIndex(bin_op.rhs).?,
});
lhs_mcv = MCValue{ .register = regs[0] };
rhs_mcv = MCValue{ .register = regs[1] };
} else if (!rhs_is_register) {
rhs_mcv = MCValue{ .register = try self.register_manager.allocReg(Air.refToIndex(bin_op.rhs).?) };
} else if (!lhs_is_register) {
lhs_mcv = MCValue{ .register = try self.register_manager.allocReg(Air.refToIndex(bin_op.lhs).?) };
}
} else {
if (!lhs_is_register) {
lhs_mcv = MCValue{ .register = try self.register_manager.allocReg(Air.refToIndex(bin_op.lhs).?) };
}
}
// Move the operands to the newly allocated registers
const branch = &self.branch_stack.items[self.branch_stack.items.len - 1];
if (lhs_mcv == .register and !lhs_is_register) {
try self.genSetReg(ty, lhs_mcv.register, lhs);
branch.inst_table.putAssumeCapacity(Air.refToIndex(bin_op.lhs).?, lhs);
}
if (rhs_mcv == .register and !rhs_is_register) {
try self.genSetReg(ty, rhs_mcv.register, rhs);
branch.inst_table.putAssumeCapacity(Air.refToIndex(bin_op.rhs).?, rhs);
}
// The destination register is not present in the cmp instruction
// The signedness of the integer does not matter for the cmp instruction
switch (rhs_mcv) {
.register => |reg| {
_ = try self.addInst(.{
.tag = .cmp_shifted_register,
.data = .{ .rrr_imm6_shift = .{
.rd = .xzr,
.rn = lhs_mcv.register,
.rm = reg,
.imm6 = 0,
.shift = .lsl,
} },
});
},
.immediate => |imm| {
_ = try self.addInst(.{
.tag = .cmp_immediate,
.data = .{ .r_imm12_sh = .{
.rn = lhs_mcv.register,
.imm12 = @intCast(u12, imm),
} },
});
return self.fail("TODO AArch64 cmp optionals", .{});
},
.Float => return self.fail("TODO AArch64 cmp floats", .{}),
else => unreachable,
}
break :result switch (signedness) {
.signed => MCValue{ .compare_flags_signed = op },
.unsigned => MCValue{ .compare_flags_unsigned = op },
};
const int_info = int_ty.intInfo(self.target.*);
if (int_info.bits <= 64) {
_ = try self.binOp(.cmp_eq, inst, lhs, rhs, int_ty, int_ty);
try self.spillCompareFlagsIfOccupied();
self.compare_flags_inst = inst;
break :result switch (int_info.signedness) {
.signed => MCValue{ .compare_flags_signed = op },
.unsigned => MCValue{ .compare_flags_unsigned = op },
};
} else {
return self.fail("TODO AArch64 cmp for ints > 64 bits", .{});
}
};
return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
}

44
src/arch/aarch64/Emit.zig
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@ -650,17 +650,32 @@ fn mirLogicalImmediate(emit: *Emit, inst: Mir.Inst.Index) !void {
fn mirAddSubtractShiftedRegister(emit: *Emit, inst: Mir.Inst.Index) !void {
const tag = emit.mir.instructions.items(.tag)[inst];
const rrr_imm6_shift = emit.mir.instructions.items(.data)[inst].rrr_imm6_shift;
const rd = rrr_imm6_shift.rd;
const rn = rrr_imm6_shift.rn;
const rm = rrr_imm6_shift.rm;
const shift = rrr_imm6_shift.shift;
const imm6 = rrr_imm6_shift.imm6;
switch (tag) {
.add_shifted_register => try emit.writeInstruction(Instruction.addShiftedRegister(rd, rn, rm, shift, imm6)),
.cmp_shifted_register => try emit.writeInstruction(Instruction.subsShiftedRegister(rd, rn, rm, shift, imm6)),
.sub_shifted_register => try emit.writeInstruction(Instruction.subShiftedRegister(rd, rn, rm, shift, imm6)),
.add_shifted_register,
.sub_shifted_register,
=> {
const rrr_imm6_shift = emit.mir.instructions.items(.data)[inst].rrr_imm6_shift;
const rd = rrr_imm6_shift.rd;
const rn = rrr_imm6_shift.rn;
const rm = rrr_imm6_shift.rm;
const shift = rrr_imm6_shift.shift;
const imm6 = rrr_imm6_shift.imm6;
switch (tag) {
.add_shifted_register => try emit.writeInstruction(Instruction.addShiftedRegister(rd, rn, rm, shift, imm6)),
.sub_shifted_register => try emit.writeInstruction(Instruction.subShiftedRegister(rd, rn, rm, shift, imm6)),
else => unreachable,
}
},
.cmp_shifted_register => {
const rr_imm6_shift = emit.mir.instructions.items(.data)[inst].rr_imm6_shift;
const rn = rr_imm6_shift.rn;
const rm = rr_imm6_shift.rm;
const shift = rr_imm6_shift.shift;
const imm6 = rr_imm6_shift.imm6;
try emit.writeInstruction(Instruction.subsShiftedRegister(.xzr, rn, rm, shift, imm6));
},
else => unreachable,
}
}
@ -896,8 +911,13 @@ fn mirMoveRegister(emit: *Emit, inst: Mir.Inst.Index) !void {
try emit.writeInstruction(Instruction.add(rr.rd, rr.rn, 0, false));
},
.mvn => {
const rr_imm6_shift = emit.mir.instructions.items(.data)[inst].rr_imm6_shift;
try emit.writeInstruction(Instruction.ornShiftedRegister(rr_imm6_shift.rd, .xzr, rr_imm6_shift.rm, rr_imm6_shift.shift, rr_imm6_shift.imm6));
const rr_imm6_logical_shift = emit.mir.instructions.items(.data)[inst].rr_imm6_logical_shift;
const rd = rr_imm6_logical_shift.rd;
const rm = rr_imm6_logical_shift.rm;
const shift = rr_imm6_logical_shift.shift;
const imm6 = rr_imm6_logical_shift.imm6;
try emit.writeInstruction(Instruction.ornShiftedRegister(rd, .xzr, rm, shift, imm6));
},
else => unreachable,
}

13
src/arch/aarch64/Mir.zig
View File

@ -249,11 +249,20 @@ pub const Inst = struct {
imm12: u12,
sh: u1 = 0,
},
/// Two registers and a shift (shift type and 6-bit amount)
///
/// Used by e.g. cmp_shifted_register
rr_imm6_shift: struct {
rn: Register,
rm: Register,
imm6: u6,
shift: bits.Instruction.AddSubtractShiftedRegisterShift,
},
/// Two registers and a shift (logical instruction version)
/// (shift type and 6-bit amount)
///
/// Used by e.g. mvn
rr_imm6_shift: struct {
rr_imm6_logical_shift: struct {
rd: Register,
rm: Register,
imm6: u6,
@ -287,7 +296,7 @@ pub const Inst = struct {
},
/// Three registers and a shift (shift type and 6-bit amount)
///
/// Used by e.g. cmp_shifted_register
/// Used by e.g. add_shifted_register
rrr_imm6_shift: struct {
rd: Register,
rn: Register,

2
test/behavior/optional.zig
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@ -33,6 +33,8 @@ test "optional pointer to size zero struct" {
}
test "equality compare optional pointers" {
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
try testNullPtrsEql();
comptime try testNullPtrsEql();
}