12995 Commits

Author SHA1 Message Date
Andrew Kelley
0c6581e01d stage2: fix memory leak when updating a function 2021-03-24 15:46:06 -07:00
Andrew Kelley
180dae4196 stage2: further cleanups regarding zir.Inst.Ref
* Introduce helper functions on Module.WipZirCode and zir.Code
 * Move some logic around
 * re-introduce ref_start_index
 * prefer usize for local variables + `@intCast` at the end.
   Empirically this is easier to optimize.
 * Avoid using mem.{bytesAsSlice,sliceAsBytes} because it incurs an
   unnecessary multiplication/division which may cause problems for the
   optimizer.
 * Use a regular enum, not packed, for `Ref`. Memory layout is
   guaranteed for enums which specify their tag type. Packed enums have
   ABI alignment of 1 byte which is too small.
2021-03-24 15:36:23 -07:00
Isaac Freund
0c601965ab
stage2: make zir.Inst.Ref a non-exhaustive enum
This provides us greatly increased type safety and prevents the common
mistake of using a zir.Inst.Ref where a zir.Inst.Index was expected or
vice-versa. It also increases the ergonomics of using the typed values
which can be directly referenced with a Ref over the previous zir.Const
approach.

The main pain point is casting between a []Ref and []u32, which could be
alleviated in the future with a new std.mem function.
2021-03-24 19:11:44 +01:00
Andrew Kelley
a1afe69395 stage2: comment out failing test cases; implement more things
* comment out the failing stage2 test cases
   (so that we can uncomment the ones that are newly passing with
   further commits)
 * Sema: implement negate, negatewrap
 * astgen: implement field access, multiline string literals, and
   character literals
 * Module: when resolving an AST node into a byte offset, use the
   main_tokens array, not the firstToken function
2021-03-23 23:13:01 -07:00
Andrew Kelley
13ced07f23 stage2: fix while loops
also start to form a plan for how inline while loops will work
2021-03-23 21:37:10 -07:00
Andrew Kelley
bf7c3e9355 astgen: fixups regarding var decls and rl_ptr 2021-03-23 16:47:41 -07:00
Andrew Kelley
be673e6793 stage2: implement inttype ZIR
also add i128 and u128 to const inst list
2021-03-23 16:12:26 -07:00
Andrew Kelley
aa46a705ad astgen: finishThenElseBlock: fix putting store_to_block_ptr in wrong block 2021-03-23 15:32:25 -07:00
Andrew Kelley
af73f79490 stage2: fix comptimeExpr and comptime function calls 2021-03-23 13:25:58 -07:00
Andrew Kelley
866be099f8 stage2: add helper functions to clean up astgen Ref/Index 2021-03-23 12:54:18 -07:00
Timon Kruiper
830143905e Sema: use correct LazySrcLoc for resolvePeerTypes 2021-03-23 11:56:06 -07:00
Timon Kruiper
7194baed66 astgen: implement typeof 2021-03-23 11:56:06 -07:00
Timon Kruiper
99cf9f8bf1 astgen: fix an issue where the alloc wasnt elided 2021-03-23 11:49:12 -07:00
Timon Kruiper
982df37135 stage2: handle void value in genRet in LLVM backend 2021-03-23 11:42:46 -07:00
Timon Kruiper
d73b0473a1 stage2: rename fail to todo in LLVM backend
This way we don't have to pass src to every function and we can simply
use the first node as the lazy source location for all the todo
errors.
2021-03-23 11:42:46 -07:00
Isaac Freund
668148549a
stage2: fix two return types to be Ref not Index
We currently have no type safety between zir.Inst.Ref, zir.Inst.Index,
and plain u32s.
2021-03-23 11:58:43 +01:00
Timon Kruiper
f3e8073e05 astgen: implement assign operations 2021-03-23 11:40:55 +01:00
Andrew Kelley
d24be85be8 stage2: fix if expressions 2021-03-22 23:47:13 -07:00
Andrew Kelley
568f333681 astgen: improve the ensure_unused_result elision 2021-03-22 18:57:46 -07:00
Andrew Kelley
2f391df2a7 stage2: Sema improvements and boolean logic astgen
* add `Module.setBlockBody` and related functions
 * redo astgen for `and` and `or` to use fewer ZIR instructions and
   require less processing for comptime known values
 * Sema: rework `analyzeBody` function. See the new doc comments in this
   commit. Divides ZIR instructions up into 3 categories:
   - always noreturn
   - never noreturn
   - sometimes noreturn
2021-03-22 17:29:56 -07:00
Isaac Freund
9f0b9b8da1
stage2: remove all async related code
The current plan is to avoid using async and related features in the
stage2 compiler so that we can bootstrap before implementing them.

Having this untested and incomplete code in the codebase increases
friction while working on stage2, in particular when preforming
larger refactors such as the current zir memory layout rework.

Therefore remove all async related code, leaving only error messages
in astgen.
2021-03-23 00:23:41 +01:00
Dimenus
240b15381d fix calculation in ensureCapacity 2021-03-22 11:58:44 -07:00
Isaac Freund
f3770dcc30
astgen: implement pointer types 2021-03-22 16:03:00 +01:00
Isaac Freund
8111453cc1
astgen: implement array types 2021-03-22 14:54:13 +01:00
Andrew Kelley
4f3071a817 cleanups from previous commit 2021-03-21 20:18:13 -07:00
jacob gw
7a55671b89 zir-memory-layout: astgen: varDecl 2021-03-21 20:10:27 -07:00
Andrew Kelley
5769c963e0 Sema: implement arithmetic 2021-03-21 19:23:12 -07:00
Andrew Kelley
07c204393f Sema: no explicit coercion needed for inline asm args
These are now done with result locations.
2021-03-21 17:55:31 -07:00
Isaac Freund
72bcdb639f
astgen: implement bool_and/bool_or 2021-03-22 00:51:25 +01:00
Isaac Freund
4cfd5f6a30 astgen: implement simple binary operators 2021-03-21 20:32:39 +01:00
Isaac Freund
310a44d5be zir: add negate/negate_wrap, implement astgen
These were previously implemented as a sub/sub_wrap instruction with a
lhs of 0. Making this separate instructions however allows us to save
some memory as there is no need to store a lhs.
2021-03-21 20:32:39 +01:00
Andrew Kelley
7800ae05a2 astgen: fix not detecting volatile asm
if only we could have compile errors for unused locals
2021-03-20 22:48:36 -07:00
Andrew Kelley
7598a00f34 stage2: fix memory management of ZIR code
* free Module.Fn ZIR code when destroying the owner Decl
 * unreachable_safe and unreachable_unsafe are collapsed into one ZIR
   instruction with a safety flag.
 * astgen: emit an unreachable instruction for unreachable literals
 * don't forget to call deinit on ZIR code
 * astgen: implement some builtin functions
2021-03-20 22:40:08 -07:00
Andrew Kelley
d8692b8bdb astgen: implement string literals 2021-03-20 21:59:28 -07:00
Andrew Kelley
8bad5dfa72 astgen: implement inline assembly 2021-03-20 21:48:35 -07:00
Andrew Kelley
260c610708 ZIR: move some un_tok tags to un_node instead
Idea here is to prefer un_node to un_tok in order to avoid unnecessary
calls to `tree.firstToken`.
2021-03-20 17:18:44 -07:00
Andrew Kelley
50010447bd astgen: implement function calls 2021-03-20 17:09:06 -07:00
jacob gw
907142a036 zir-memory-layout: remove all absolute src consts
this is to prevent future bugs
2021-03-20 15:56:59 -07:00
jacob gw
12eeb18a26 zir-memory-layout: astgen: more instructions 2021-03-20 15:56:59 -07:00
Timon Kruiper
a710368054 stage2: restructure LLVM backend
The LLVM backend is now structured into 3 different structs, namely
Object, DeclGen and FuncGen. Object represents an object that is
generated by the LLVM backend. DeclGen is responsible for generating
a decl and FuncGen is responsible for generating llvm instructions
from tzir in a function.
2021-03-20 15:10:44 -07:00
Andrew Kelley
56677f2f2d astgen: support blocks
We are now passing this test:

```zig
export fn _start() noreturn {}
```

```
test.zig:1:30: error: expected noreturn, found void
```

I ran into an issue where we get an integer overflow trying to compute
node index offsets from the containing Decl. The problem is that the
parser adds the Decl node after adding the child nodes. For some things,
it is easy to reserve the node index and then set it later, however, for
this case, it is not a trivial code change, because depending on tokens
after parsing the decl determines whether we want to add a new node or
not.

Possible strategies here:

1. Rework the parser code to make sure that Decl nodes are before
   children nodes in the AST node array.

2. Use signed integers for Decl node offsets.

3. Just flip the order of subtraction and addition. Expect Decl Node
   index to be greater than children Node indexes.

I opted for (3) because it seems like the simplest thing to do. We'll
want to unify the logic for computing the offsets though because if the
logic gets repeated, it will probably get repeated wrong.
2021-03-19 23:15:18 -07:00
Andrew Kelley
937c43ddf1 stage2: first pass at repairing ZIR printing 2021-03-19 19:33:11 -07:00
Andrew Kelley
0357cd8653 Sema: allocate inst_map with arena where appropriate 2021-03-19 15:31:50 -07:00
Andrew Kelley
81a935aef8 stage2: fix some math oopsies and typos 2021-03-19 15:19:47 -07:00
Andrew Kelley
132df14ee1 stage2: fix export source locations not being relative to Decl 2021-03-19 14:59:46 -07:00
jacob gw
a4f0ccdfe4 zir-memory-layout: astgen: literals and *, &
this was pretty low hanging fruit
2021-03-19 14:50:15 -07:00
jacob gw
c50397c268 llvm backend: use new srcloc
this allows to compile with ninja
2021-03-19 14:46:37 -07:00
jacob gw
e9810d9e79 zir-memory-layout: astgen: fill in identifier 2021-03-19 14:43:08 -07:00
Andrew Kelley
abdbc11c7e stage2: codegen: update asm IR to new names 2021-03-18 22:54:59 -07:00
Andrew Kelley
bd2154da3d stage2: the code is compiling again
(with a lot of things commented out)
2021-03-18 22:48:28 -07:00