17897 Commits

Author SHA1 Message Date
John Schmidt
e4d427f12e refactor: add Sema.addFieldErrNote 2022-04-03 13:49:34 +02:00
John Schmidt
b922caf169 sema: add compile error for missing/extra enum fields in union decl 2022-04-03 13:49:34 +02:00
John Schmidt
f7f4702795 sema: add more info to error messages for enum->union coercion 2022-04-03 13:49:34 +02:00
John Schmidt
8f0dac01ef sema: add more info to error message for invalid comptime union field access 2022-04-03 13:49:34 +02:00
Andrew Kelley
91eb1af917 stage2: more resilient error handling
* If more than one error is reported for the same Decl, the first error
   message is kept and the second one discarded.
 * Prevent functions from being sent to codegen backends if there were
   any errors resolving any of their parameter types or return type.
2022-04-02 19:18:41 -07:00
Andrew Kelley
3432e66faf stage2: remove dependencies on async functions
This commit removes the tiny amount of dependency on async/await that
the self-hosted compiler has so that it can self-host before async/await
language features are working.
2022-04-02 19:18:41 -07:00
Andrew Kelley
843d5adcd6 std.ArrayHashMap: lazier verifyContext calls
Companion commit to b45c6c757cb4a16f5021c8bf057d14183036f14c.

Related: #11367
2022-04-02 19:18:41 -07:00
Andrew Kelley
3b32e0be31 behavior tests: disable failing stage1 test
I forgot to check that the new behavior tests also pass in stage1. One
of them does not.

Fixes regression from 4618c41fa6ca70f06c7e65762d2f38d57b00818c.
2022-04-02 19:02:29 -07:00
Andrew Kelley
4618c41fa6 Sema: mechanism for converting comptime breaks to runtime
closes #11369
2022-04-02 18:30:44 -07:00
Veikka Tuominen
83bb98e13b stage2 llvm: properly align error union payload 2022-04-02 19:31:32 -04:00
Luuk de Gram
a0a587ff85 wasm: Enable passing behavior tests
This shuffles some tests do ensure the new instructions are tested for the wasm backend,
by moving vectors into their own tests as well as move the f16 test cases as those require
special operating also.
2022-04-02 21:54:01 +02:00
Luuk de Gram
2c40b37f79 wasm: Implement @ctz for bitsize <= 64
Implements the `ctz` AIR instruction for integers with bitsize <= 64.
When the bitsize of the integer does not match the bitsize of a wasm type,
we first XOR the value with the value of (1<<bitsize) to set the right bits
and ensure we will only count the trailing zeroes of the integer with the correct bitsize.
2022-04-02 21:54:01 +02:00
Luuk de Gram
bd27fe2bf5 wasm: Implement @clz
Implements the `clz` AIR instruction for integers with bitsize <= 64.
When the bitsize of the integer is not the same as wasm's bitsize,
we substract the difference in bits as those will always be 0 for the integer, but should
not be counted towards the end result. We also wrap the result to ensure it fits
in the result type as documented in the language reference.
2022-04-02 21:54:01 +02:00
Luuk de Gram
5ba03369ee wasm: Implement @mulAdd for f32, f64
This implements the `mul_add` AIR instruction for floats of bitsize 32 and 64.
f16's will require us being able to extend and truncate f16's to correctly
store and load them without losing the accuracy.
2022-04-02 21:54:01 +02:00
Luuk de Gram
219fa192c6 wasm: Implement @maximum & @minimum
This implements the `max` and `min` AIR instructions by checking
whether LHS is great/lesser than RHS. If that's the case, we assign
LHS to the result, otherwise assign RHS to it instead.
2022-04-02 21:54:01 +02:00
Jakub Konka
3ee44ce949
Merge pull request #11373 from joachimschmidt557/stage2-arm
stage2 ARM: implement overflow operations for ints <= 32 bits
2022-04-02 10:52:34 +02:00
joachimschmidt557
8c12ad98b8
stage2 ARM: implement mul_with_overflow for ints <= 32 bits 2022-04-01 22:51:18 +02:00
joachimschmidt557
c4778fc029
stage2 ARM: implement mul_with_overflow for ints <= 16 bits 2022-04-01 22:02:56 +02:00
joachimschmidt557
77e70189f4
stage2 ARM: implement shl_with_overflow for ints <= 32 bits 2022-04-01 22:02:56 +02:00
joachimschmidt557
37a8c28802
stage2 ARM: implement add/sub_with_overflow for ints < 32 bits 2022-04-01 22:02:56 +02:00
joachimschmidt557
7285f0557c
stage2 ARM: implement add/sub_with_overflow for u32/i32 2022-04-01 22:02:55 +02:00
joachimschmidt557
e2e69803dc
stage2 ARM: change binOp lowering mechanism to use Mir tags
The Air -> Mir correspondence is not 1:1, so this better represents
what Mir insruction we actually want to generate.
2022-04-01 22:02:51 +02:00
Jakub Konka
8b5d5f44e2 macho: set CS_LINKER_SIGNED flag in code signature generated by zld
This way, if the user wants to use `codesign` (or other tool) they
will not be forced to `-f` force signature update. This matches
the behavior promoted by Apple's `ld64` linker.
2022-04-01 14:33:37 +02:00
Jakub Konka
fd29ddc06c x64: implement add/sub with wrapping and xor op 2022-04-01 11:37:18 +02:00
Andrew Kelley
87179d91a7 stage2: hook up Sema to the progress bar 2022-04-01 00:17:02 -07:00
Andrew Kelley
b45c6c757c std.hash_map: workaround for circular dependency
See #11367

It's debatable whether this ends up being a legitimate compile error or
whether the lang spec allows this test case. For now this workaround
seems very reasonable; delaying comptime execution of `verifyContext`
until the struct is instantiated.
2022-04-01 00:17:02 -07:00
Andrew Kelley
26253acf1d AstGen: use block_inline and break_inline consistently
These are more efficiently semantically analyzed. More importantly, if
they don't match, we get a crash in Sema.

Missing places prior to this commit:
 * labeled blocks
 * `break` and `continue` on comptime (not inline) loops
 * `if`, `try`, `orelse`, and `catch` inside comptime scopes
2022-03-31 23:47:34 -07:00
Andrew Kelley
ecd756834b CI: update CLI invokation
243afdcdf57d74a184784551aebe58062e5afc03 removed `-Dskip-compile-errors`
and added `-Dskip-stage`.
2022-03-31 16:06:50 -07:00
Andrew Kelley
243afdcdf5 test harness improvements
* `-Dskip-compile-errors` is removed; `-Dskip-stage1` is added.
 * Use `std.testing.allocator` instead of a new instance of GPA.
   - Fix the memory leaks this revealed.
 * Show the file name when it is not parsed correctly such as when the
   manifest is missing.
   - Better error messages when test files are not parsed correctly.
 * Ignore unknown files such as swap files.
 * Move logic from declarative file to the test harness implementation.
 * Move stage1 tests to stage2 tests where appropriate.
2022-03-31 15:10:31 -07:00
Andrew Kelley
df1ba38a88 AstGen: fix treating noreturn instructions as void
Fixes regression introduced in cf4aad4858ac61b4814d8f021c8eae22ee7f63e6.
2022-03-31 15:06:12 -07:00
Andrew Kelley
b6133931d0 Sema: fix segfault during resolveInferredErrorSet
There was a simple missing check of adding an inferred error set to
itself, in which case we should not try to mutate the hash map while
iterating over it.
2022-03-31 12:25:48 -07:00
Andrew Kelley
cf4aad4858 AstGen: fix referencing unreferencable instructions
Sema avoids adding map entries for certain instructions such as
`set_eval_branch_quota` and `atomic_store`. This means that result
location semantics in AstGen must not emit any instructions that attempt
to use the result of any of these instructions.

This commit makes AstGen replace such instructions with
`Zir.Inst.Ref.void_value` if their result value ends up being
referenced.

This fixes a compiler crash when running std lib atomic tests.
2022-03-30 23:19:10 -07:00
Meghan Denny
08565b23f9 stage2: fix print_zir for .builtin_src 2022-03-31 02:12:44 -04:00
Veikka Tuominen
75c2cff40e stage2: handle assembly input names 2022-03-31 01:33:28 -04:00
Andrew Kelley
6655c6092e std.base64: upgrade to new function pointer semantics 2022-03-30 20:38:01 -07:00
Andrew Kelley
02d69f5009 Sema: fix usingnamespace decl Value in wrong arena
closes #11297
2022-03-30 17:24:01 -07:00
James Mintram
5d5b1b68fc Remove a std.debug.print from the dwarf.zig file
This was causing freestanding builds to fail due to the
use of `std.debug.print`
2022-03-30 19:35:20 -04:00
Veikka Tuominen
3c64c519e6
Merge pull request #11246 from jmc-88/cbe-asm
CBE: improve support for asm inputs
2022-03-31 00:04:04 +03:00
Andrew Kelley
d227f76afb std.zig.Ast: fix escaped capture of by-value parameters 2022-03-30 11:52:10 -07:00
Andrew Kelley
47dfaf47b8 stage2: test compile errors independently
Until we land some incremental compilation bug fixes, this prevents CI
failures when running the compile errors test cases.
2022-03-30 11:22:27 -07:00
Jakub Konka
f5d9160f1b dwarf: pass DeclState around instead of storing a temp global in Dwarf
Avoids many pitfalls connected with premature/early return in case
there are errors with Decl, etc. This is effectively bringing back
the old design however in a much nicer packaging, where every
mechanism related to tracking Decl's debug info is now nicely
wrapped in a single struct (aka the `DeclState`). This includes
relocation table, type arena, etc. It is now the caller's
responsibility to deinit the state (so that no memory is leaked)
after `Decl` has been analysed (or errored out). The caller here
is typically a linker such as `Elf` or `MachO`.
2022-03-30 14:21:13 -04:00
Meghan
b73cf97c93
replace other uses of std.meta.Vector with @Vector (#11346) 2022-03-30 14:12:14 -04:00
Jakub Konka
b153e156b1
Merge pull request #11342 from ziglang/stage2-x64-mul-div
x64: use all available registers (caller and callee), and fix how we multiply (fixes @mulWithOverflow for byte-size operands)
2022-03-30 11:22:35 +02:00
Daniele Cocca
907dc1e13f CBE: improve support for asm inputs
This is not complete support for asm expressions, but allows a few more
test cases from test/behavior/asm.zig to pass. Since the non-register
inputs are named `input_${n}` they can cause name collisions: I'm
wrapping the asm expressions in their own block to prevent that.

Contextually, this change also makes test/behavior/asm.zig run for
stage2, but skips individual tests for most backends (I only verified
the C and LLVM backends successfully run one new test case) and the
entire test file for aarch64, where it's running into preexisting
shortcomings.
2022-03-30 12:10:02 +03:00
Daniele Cocca
ebafdb958c AstGen: don't coerce inputs to usize in asmExpr
Instead, use ResultLoc.none to allow for the expression type to be
inferred [^1]. This effectively moves the type coercion to Sema, in
order to turn comptime values into usable values for the backends to
consume. Right now the coercion is applies as comptime_int -> usize and
comptime_float -> f64, as an arbitrary choice.

[^1]: 9f25c8140c/src/AstGen.zig (L207-L208)
2022-03-30 11:57:16 +03:00
Daniele Cocca
633fe41a2c Sema: allow comptime blocks for global assembly
An assembly expression in a comptime block is legal Zig in the case of
global assembly [^1]. Instead of unconditionally asserting that the
expression lives in a runtime block, here we assert that if the
expression lives in a comptime block it must be outside of function
scope.

[^1]: https://ziglang.org/documentation/0.9.1/#Global-Assembly
2022-03-30 11:57:15 +03:00
Daniele Cocca
5d5282b5f1 AstGen: support local var references for outputs 2022-03-30 11:57:15 +03:00
Andrew Kelley
c21f046a8b Sema: enhance is_non_err to be comptime more often
* Sema: store the precomputed monomorphed_funcs hash inside Module.Fn.
   This is important because it may be accessed when resizing monomorphed_funcs
   while this Fn has already been added to the set, but does not have the
   owner_decl, comptime_args, or other fields populated yet.
 * Sema: in `analyzeIsNonErr`, take advantage of the AIR tag being
   `wrap_errunion_payload` to infer that `is_non_err` is comptime true
   without performing any error set resolution.
   - Also add some code to check for empty inferred error sets in this
     function. If necessary we do resolve the inferred error set.
 * Sema: queue full type resolution of payload type when
   `wrap_errunion_payload` AIR instruction is emitted. This ensures the
   backend may check the alignment of it.
 * Sema: resolveTypeFully now additionally resolves comptime-only
   status.

closes #11306
2022-03-30 00:47:55 -07:00
Andrew Kelley
05947ea870 stage2: implement @intToError with safety
This commit introduces a new AIR instruction `cmp_lt_errors_len`. It's
specific to this use case for two reasons:

 * The total number of errors is not stable during semantic analysis; it
   can only be reliably checked when flush() is called. So the backend
   that is lowering the instruction must emit a relocation of some kind
   and then populate it during flush().
 * The fewer AIR instructions in memory, the better for compiler
   performance, so we squish complex meanings into AIR tags without
   hesitation.

The instruction is implemented only in the LLVM backend so far. It does
this by creating a simple function which is gutted and re-populated
with each flush().

AstGen now uses ResultLoc.coerced_ty for `@intToError` and Sema does the
coercion.
2022-03-29 22:19:06 -07:00
Andrew Kelley
83617eac59 std: avoid referencing event loop when io_mode is blocking
This prevents unwanted symbols from ending up in the output binary.
2022-03-29 22:16:43 -07:00