102 Commits

Author SHA1 Message Date
Ali Cheraghi
dec1163fbb
all: replace all @Type usages
Co-authored-by: Matthew Lugg <mlugg@mlugg.co.uk>
2025-11-22 22:42:38 +00:00
Jacob Young
402c14f86a
aarch64: implement optional comparisons 2025-10-30 09:31:30 +00:00
Justus Klausecker
0ecbd5a0e1 address comments 2025-08-07 13:58:49 +02:00
Justus Klausecker
ba549a7d67 Add support for both '_' and 'else' prongs at the same time in switch statements
If both are used, 'else' handles named members and '_' handles
unnamed members. In this case the 'else' prong will be unrolled
to an explicit case containing all remaining named values.
2025-08-07 13:58:47 +02:00
Justus Klausecker
1d9b1c0212 Permit explicit tags with '_' switch prong
Mainly affects ZIR representation of switch_block[_ref]
and special prong (detection) logic for switch.
Adds a new SpecialProng tag 'absorbing_under' that allows
specifying additional explicit tags in a '_' prong which
are respected when checking that every value is handled
during semantic analysis but are not transformed into AIR
and instead 'absorbed' by the '_' branch.
2025-08-07 13:57:57 +02:00
Jacob Young
c334956a54 aarch64: workaround some optional/union issues 2025-07-28 09:03:17 -07:00
Andrew Kelley
da408bd6fc
Merge pull request #24585 from jacobly0/aarch64
aarch64: more progress
2025-07-27 00:17:19 -07:00
Jacob Young
7894703ee7 aarch64: implement more optional/error union/union support 2025-07-26 21:39:50 -04:00
Jacob Young
7c349da49c aarch64: implement complex switch prongs 2025-07-26 16:08:40 -04:00
Jacob Young
68cfa736df x86_64: fix switch on mod result
Closes #24541
2025-07-26 06:24:03 -04:00
Jacob Young
5060ab99c9 aarch64: add new from scratch self-hosted backend 2025-07-22 19:43:47 -07:00
Ali Cheraghi
872f68c9cb
rename spirv backend name
`stage2_spirv64` -> `stage2_spirv`
2025-06-16 13:22:19 +03:30
Jacob Young
37f763560b x86_64: fix switch dispatch bug
Also closes #23902
2025-06-06 23:42:15 -07:00
Jacob Young
1eb5d70d12 x86_64: fix switch on big ints 2025-04-09 20:14:12 -04:00
Ali Cheraghi
aec0f9b3e7
test: skip failing tests with spirv-vulkan 2025-02-24 19:39:42 +01:00
Pavel Verigo
b25d93e7d9 stage2-wasm: implement switch_dispatch + handle > 32 bit integers in switches
Updated solution is future proof for arbitary size integer handling for both strategies .br_table lowering if switch case is dense, .br_if base jump table if values are too sparse.
2025-02-22 18:34:00 -05:00
Robin Voetter
86b88ea7da
spirv: skip range switch tests
This is not yet implemented
2024-10-13 01:58:11 +02:00
mlugg
03c363300f AstGen: do not allow unlabeled break to exit a labeled switch
`break`ing from something which isn't a loop should always be opt-in.
This was a bug in #21257.
2024-09-12 22:52:23 +01:00
mlugg
b7a55cd6c3
AstGen: allow breaking from labeled switch
Also, don't use the special switch lowering for errors if the switch
is labeled; this isn't currently supported. Related: #20627.
2024-09-01 18:31:01 +01:00
David Rubin
8da212c11b
riscv: update tests and fix reuse bug 2024-07-26 04:19:58 -07:00
David Rubin
1a7d89a84d
riscv: clean up and unify encoding logic 2024-07-26 04:19:13 -07:00
David Rubin
8d30fc45c4
riscv: implement more operators
we can run `std.debug.print` now, with both run-time strings and integers!
2024-07-26 04:05:39 -07:00
David Rubin
7a02878f4e
riscv: truncate airStructFieldVal result 2024-07-14 23:02:33 -07:00
David Rubin
4fd8900337
riscv: rewrite "binOp"
Reorganize how the binOp and genBinOp functions work.

I've spent quite a while here reading exactly through the spec and so many
tests are enabled because of several critical issues the old design had.

There are some regressions that will take a long time to figure out individually
so I will ignore them for now, and pray they get fixed by themselves. When
we're closer to 100% passing is when I will start diving into them one-by-one.
2024-06-13 02:24:39 -07:00
David Rubin
7ed2f2156f
riscv: fix register clobber in certain edge cases 2024-06-13 02:21:38 -07:00
David Rubin
381a1043eb
ZigObject: enforce min function alignement on riscv 2024-06-13 02:21:38 -07:00
David Rubin
05de6c279b
riscv: std.fmt.format running
- implements `airSlice`, `airBitAnd`, `airBitOr`, `airShr`.

- got a basic design going for the `airErrorName` but for some reason it simply returns
empty bytes. will investigate further.

- only generating `.got.zig` entries when not compiling an object or shared library

- reduced the total amount of ops a mnemonic can have to 3, simplifying the logic
2024-06-13 02:20:47 -07:00
David Rubin
004d0c8978
riscv: switch progress + by-ref return progress 2024-06-13 02:19:38 -07:00
David Rubin
d9e0cafe64 riscv: add stage2_riscv to test matrix and bypass failing tests 2024-05-11 02:17:24 -07:00
Robin Voetter
ac16545895
spirv: enable passing tests 2024-04-06 13:52:48 +02:00
Ali Chraghi
0f75143c62 spirv: implement @divFloor, @floor and @mod 2024-04-06 08:50:02 +03:30
mlugg
f3227598eb Sema: reset block error return trace index between cases
Resolves: #19210
2024-03-08 07:30:32 -08:00
Jacob Young
aa688567f5 Air: replace .dbg_inline_* with .dbg_inline_block
This prevents the possibility of not emitting a `.dbg_inline_end`
instruction and reduces the allocation requirements of the backends.

Closes #19093
2024-03-02 21:19:34 -08:00
John Schmidt
7cb227ab67 Polish a few tests in switch.zig
- Return `error.TestFailed` instead of panicing
- Use `comptime assert` for type checks so that errors surface at
  compile time
2024-02-08 23:49:03 +01:00
John Schmidt
0d1baf0c61 Improvements after code review 2024-02-08 23:49:03 +01:00
John Schmidt
dbcd53def0 Preserve field alignment in union pointer captures 2024-02-08 23:49:03 +01:00
dweiller
8108c9f4d2 test/behavior: replace all 'comptime expect' with 'comptime assert' 2024-01-15 20:55:01 +11:00
Veikka Tuominen
804cee3b93 categorize behavior/bugs/<issueno>.zig tests 2024-01-06 16:49:41 -08:00
mlugg
9c16b2370d
test: update behavior to silence 'var is never mutated' errors 2023-11-19 09:57:03 +00:00
mlugg
c1c9bc0c41 Sema: do not assume switch item indices align with union field indices
Resolves: #17754
2023-10-28 06:30:28 +01:00
Ali Chraghi
e5d5c1d423 spirv: switch on bool 2023-10-18 02:31:16 +03:30
Robin Voetter
faad97edff
spirv: update failing / passing tests
Some tests are now failing due to debug info changes, some tests
now pass due to improved compiler functionality.
2023-10-15 20:08:18 +02:00
Robin Voetter
075584a4d7 spirv: enable passing tests 2023-09-23 12:36:56 -07:00
Robin Voetter
79f7481575 spirv: disable failing tests 2023-09-23 12:36:44 -07:00
Andrew Kelley
407d91f7a7 add behavior test for switch nested break
closes #10196
2023-07-26 19:02:02 -07:00
mlugg
f26dda2117 all: migrate code to new cast builtin syntax
Most of this migration was performed automatically with `zig fmt`. There
were a few exceptions which I had to manually fix:

* `@alignCast` and `@addrSpaceCast` cannot be automatically rewritten
* `@truncate`'s fixup is incorrect for vectors
* Test cases are not formatted, and their error locations change
2023-06-24 16:56:39 -07:00
kcbanner
5fc5e4fbe0 sema: Fix overflow when analyzing an inline switch prong range that ends on the maximum value of the switched type 2023-06-23 18:28:33 -07:00
Eric Joldasov
50339f595a all: zig fmt and rename "@XToY" to "@YFromX"
Signed-off-by: Eric Joldasov <bratishkaerik@getgoogleoff.me>
2023-06-19 12:34:42 -07:00
Eric Joldasov
d884d7050e
all: replace comptime try with try comptime
Signed-off-by: Eric Joldasov <bratishkaerik@getgoogleoff.me>
2023-06-13 23:46:58 +06:00
mlugg
bcb673d94a
Sema: resolve union payload switch captures with peer type resolution
This is a bit harder than it seems at first glance. Actually resolving
the type is the easy part: the interesting thing is actually getting the
capture value. We split this into three cases:

* If all payload types are the same (as is required in status quo), we
  can just do what we already do: get the first field value.
* If all payloads are in-memory coercible to the resolved type, we still
  fetch the first field, but we also emit a `bitcast` to convert to the
  resolved type.
* Otherwise, we need to handle each case separately. We emit a nested
  `switch_br` which, for each possible case, gets the corresponding
  union field, and coerces it to the resolved type. As an optimization,
  the inner switch's 'else' prong is used for any peer which is
  in-memory coercible to the target type, and the bitcast approach
  described above is used.

Pointer captures have the additional constraint that all payload types
must be in-memory coercible to the resolved type.

Resolves: #2812
2023-06-13 12:55:22 +01:00