3477 Commits

Author SHA1 Message Date
Andrew Kelley
d4bf44024a
Merge pull request #10019 from mattbork/ret-fixes
astgen.zig: fixes for error propagation `ret` and return types in `fnDecl` and `fnProtoExpr`
2021-10-25 13:40:03 -04:00
Isaac Freund
f7b090d707 std.log: simplify to 4 distinct log levels
Over the last year of using std.log in practice, it has become clear to
me that having the current 8 distinct log levels does more harm than
good. It is too subjective which level a given message should have which
makes filtering based on log level weaker as not all messages will have
been assigned the log level one might expect.

Instead, more granular filtering should be achieved by leveraging the
logging scope feature. Filtering based on a combination of scope and log
level should be sufficiently powerful for all use-cases.

Note that the self hosted compiler has already limited itself to 4
distinct log levels for many months and implemented granular filtering
based on both log scope and level. This has worked very well in practice
while working on the self hosted compiler.
2021-10-24 15:04:29 -04:00
Jakub Konka
6cf5305e47 macho: remove unresolved ref in the correct place
* without this, when an included relocatable references a common symbol
  from another translation unit would not be correctly removed from
  the unresolved lookup table triggering a misleading assertion down
  the line
* assert upon removal that we indeed removed a ref instead of silently
  ignoring in debug
* add test case that covers this issue
2021-10-24 21:01:04 +02:00
LemonBoy
811766e1cf stage1/stage2: Simplify divTrunc impl
According to the documentation, `divTrunc` is "Truncated division.
Rounds toward zero". Lower it as a straightforward fdiv + trunc sequence
to make it behave as expected with mixed positive/negative operands.

Closes #10001
2021-10-24 17:11:43 +02:00
Matthew Borkowski
9c5b852f9b astgen.zig: emit ZIR for callconv before return type in fnDecl and fnProtoExpr 2021-10-23 22:52:43 -04:00
Andrew Kelley
22b4c9e1a9 stage2: implement more C pointer Sema and comptime ptr arith 2021-10-23 19:47:32 -07:00
Andrew Kelley
d97928bf52 stage2: implement aligned variables and @alignCast
* Sema: implement zirAllocExtended
 * Sema: implement zirAlignCast
2021-10-22 17:50:36 -07:00
Andrew Kelley
01c1f41520 stage2: slice and alignment fixes
* Fix backend using wrong union field of the slice instruction.
 * LLVM backend properly sets alignment on global variables.
 * Sema: add coercion for *T to *[1]T
 * Sema: pointers to Decls with explicit alignment now have alignment
   metadata in them.
2021-10-22 17:12:12 -07:00
Andrew Kelley
f0dcdd7931 stage2: fix Decl addrspace being undefined 2021-10-22 15:53:59 -07:00
Andrew Kelley
069c83d58c stage2: change @bitCast to always be by-value
After a discussion about language specs, this seems like the best way to
go, because it's simpler to reason about both for humans and compilers.

The `bitcast_result_ptr` ZIR instruction is no longer needed.

This commit also implements writing enums, arrays, and vectors to
virtual memory at compile-time.

This unlocked some more of compiler-rt being able to build, which
in turn unlocks saturating arithmetic behavior tests.

There was also a memory leak in the comptime closure system which is now
fixed.
2021-10-22 15:35:35 -07:00
Andrew Kelley
895aea0b63 Sema: fix type checking of @intToFloat operands
There was a typo and they were backwards.
2021-10-21 23:01:05 -07:00
Andrew Kelley
0a6851cc6d stage2: implement comptime loads through casted pointers 2021-10-21 22:56:11 -07:00
Andrew Kelley
7f70c27e9d stage2: more division support
AIR:
 * div is renamed to div_trunc.
 * Add div_float, div_floor, div_exact.
   - Implemented in Sema and LLVM codegen. C backend has a stub.

Improvements to std.math.big.Int:
 * Add `eqZero` function to `Mutable`.
 * Fix incorrect results for `divFloor`.

Compiler-rt:
 * Add muloti4 to the stage2 section.
2021-10-21 19:05:26 -07:00
Robin Voetter
a3c9bfef30 stage2: truncation
* Also fixes a related case where big int truncate would assume that the
input fits in the output limbs buffer
2021-10-21 20:10:27 -04:00
Andrew Kelley
a0e195120d stage2: implement slicing
* New AIR instruction: slice, which constructs a slice out of a pointer
   and a length.
 * AstGen: use `coerced_ty` for start and end expressions, use `none`
   for the sentinel, and don't try to load the result of the slice
   operation because it returns a by-value result.
 * Sema: pointer arithmetic is extracted into analyzePointerArithmetic
   and it is used by the implementation of slice.
   - Also I implemented comptime pointer addition.
 * Sema: extract logic into analyzeSlicePtr, analyzeSliceLen and use them
   inside the slice semantic analysis.
   - The approach in stage2 is much cleaner than stage1 because it uses
     more granular analysis calls for obtaining the slice pointer, doing
     arithmetic on it, and checking if the length is comptime-known.
 * Sema: use the slice Value Tag for slices when doing coercion from
   pointer-to-array.
 * LLVM backend: detect when emitting a GEP instruction into a
   pointer-to-array and add the extra index that is required.
 * Type: ptrAlignment for c_void returns 0.
 * Implement Value.hash and Value.eql for slices.
 * Remove accidentally duplicated behavior test.
2021-10-20 21:45:11 -07:00
Andrew Kelley
c8ded2f9c9 stage2: implement big int to float conversion 2021-10-20 16:41:08 -07:00
Andrew Kelley
4cb5fed10b AstGen: make the index variable of inline for a alloc_comptime
Before it was being emitted as an `alloc` which caused inline for loops
to not work correctly.
2021-10-20 15:34:10 -07:00
Stéphan Kochen
d949180ab0 translate-c: create inline fn for always_inline 2021-10-20 17:58:30 -04:00
Andrew Kelley
ed2a5081e1 stage2: LLVM backend: implement switch_br 2021-10-20 14:10:37 -07:00
Andrew Kelley
dfb3231959 stage2: implement switching on unions
* AstGen: Move `refToIndex` and `indexToRef` to Zir
 * ZIR: the switch_block_*_* instruction tags are collapsed into one
   switch_block tag which uses 4 bits for flags, and reduces the
   scalar_cases_len field from 32 to 28 bits.
   This freed up more ZIR tags, 2 of which are now used for
   `switch_cond` and `switch_cond_ref` for producing the switch
   condition value. For example, for union values it returns the
   corresponding enum value.
 * switching with multiple cases and ranges is not yet supported because
   I want to change the ZIR encoding to store index pointers into the
   extra array rather than storing prong indexes. This will avoid O(N^2)
   iteration over prongs.
 * AstGen now adds a `switch_cond` on the operand and then passes the
   result of that to the `switch_block` instruction.
 * Sema: partially implement `switch_capture_*` instructions.
 * Sema: `unionToTag` notices if the enum type has only one possible value.
2021-10-19 20:22:47 -07:00
Matthew Borkowski
2d7b55aa0a translate_c: prevent a while under an if from stealing the else 2021-10-19 13:48:09 -04:00
Matthew Borkowski
135cb529de astgen.zig: fix emitting wrong error unwrapping instructions in tryExpr 2021-10-19 13:44:48 -04:00
Matthew Borkowski
79a3dfcfd8 astgen.zig: fix false positive in breakExpr's checking for store_to_block_ptr 2021-10-18 13:18:47 -04:00
Andrew Kelley
7b00bef6bf Sema: resolveTypeFields before accessing type fields 2021-10-17 21:53:59 -07:00
Meghan Denny
0ef2e2520a stage2: implement @hasField
struct and union are kept in stage1 because struct/unionFieldCount are returning zero
2021-10-17 21:42:22 -07:00
Meghan Denny
7d0a74456b alphebetize behavior tests 2021-10-17 21:42:22 -07:00
Andrew Kelley
40cbf525f7 stage2: implement coercion from null to C pointer 2021-10-17 19:10:49 -07:00
Andrew Kelley
ad17108bdd
Merge pull request #9960 from Snektron/bit-not
Some not and vector stuff
2021-10-17 21:59:10 -04:00
Andrew Kelley
e9d1e5e533 stage2: LLVM backend: lower constant field/elem ptrs 2021-10-17 17:02:20 -07:00
Andrew Kelley
07691db3ae stage2: fix handling of error unions as return type
* LLVM backend: fix phi instruction not respecting `isByRef`
   - Also fix `is_non_null` not respecting `isByRef`
 * Type: implement abiSize for error unions
2021-10-17 15:36:12 -07:00
Andrew Kelley
6534f2ef4f stage2: implement error wrapping
* Sema: fix returned operands not coercing to the function return type
   in some cases.
   - When returning an error or an error union from a function with an
     inferred error set, it will now populate the inferred error set.
   - Implement error set coercion for the common case of inferred error
     set to inferred error set, without forcing a full resolution.
 * LLVM backend: update instruction lowering that handles error unions
   to respect `isByRef`.
   - Also implement `wrap_err_union_err`.
2021-10-17 14:55:32 -07:00
Robin Voetter
9336a87452 stage2: bitNot 2021-10-17 20:33:04 +02:00
Andrew Kelley
fdd11f6cee Sema: coercion from error sets to anyerror 2021-10-16 12:41:03 -07:00
Andrew Kelley
82ec56e47e
Merge pull request #9954 from Snektron/shifts
Big int saturating left shift
2021-10-16 15:06:13 -04:00
Meghan Denny
6f30c8c098 elevate more passing tests 2021-10-16 15:04:48 -04:00
Robin Voetter
f6bf24b2f3 stage2: comptime saturating shl 2021-10-16 11:32:05 +02:00
Meghan
1df926b24e stage2: @hasDecl is passing 2021-10-16 04:09:16 -04:00
Andrew Kelley
682cdeceaa stage2: optional comparison and 0-bit payloads
* Sema: implement peer type resolution for optionals and null.
 * Rename `Module.optionalType` to `Type.optional`.
 * LLVM backend: re-use anonymous values. This is especially useful when
   isByRef()=true because it means re-using the same generated LLVM globals.
 * LLVM backend: rework the implementation of is_null and is_non_null
   AIR instructions. Generate slightly better LLVM code, and also fix
   the behavior for optionals whose payload type is 0-bit.
 * LLVM backend: improve `cmp` AIR instruction lowering to support
   pointer-like optionals.
 * `Value`: implement support for equality-checking optionals.
2021-10-15 18:37:09 -07:00
Andrew Kelley
186126c2a4 stage2: make hasCodeGenBits() always true for pointers
* LLVM backend: The `alloc` AIR instruction as well as pointer
   constants which point to a 0-bit element type now call a common
   codepath to produce a `*const llvm.Value` which is a non-zero pointer
   with a bogus-but-properly-aligned address.
 * LLVM backend: improve the lowering of optional types.
 * Type: `hasCodeGenBits()` now returns `true` for pointers even when
   it returns `false` for their element types.

Effectively, #6706 is now implemented in stage2 but not stage1.
2021-10-15 17:17:59 -07:00
travisstaloch
16ac034a32
Sat shl neg rhs (#9949)
* saturating shl - check for negative rhs at comptime

- adds expected compile_errors case for negative rhs

* add expected compile error for sat shl assign
2021-10-15 13:56:27 -04:00
Andrew Kelley
cacd5366a6 stage2: LLVM backend: implement wrap_optional AIR
and move over some passing tests
2021-10-14 22:16:26 -07:00
Andrew Kelley
55eea3b045 stage2: implement @minimum and @maximum, including vectors
* std.os: take advantage of `@minimum`. It's probably time to
   deprecate `std.min` and `std.max`.
 * New AIR instructions: min and max
 * Introduce SIMD vector support to stage2
 * Add `@Type` support for vectors
 * Sema: add `checkSimdBinOp` which can be re-used for other arithmatic
   operators that want to support vectors.
 * Implement coercion from vectors to arrays.
   - In backends this is handled with bitcast for vector to array,
     however maybe we want to reduce the amount of branching by
     introducing an explicit AIR instruction for it in the future.
 * LLVM backend: implement lowering vector types
 * Sema: Implement `slice.ptr` at comptime
 * Value: improve `numberMin` and `numberMax` to support floats in
   addition to integers, and make them behave properly in the presence
   of NaN.
2021-10-14 21:17:30 -07:00
Andrew Kelley
8b88274781 stage2: improved union support
* `Module.Union.getFullyQualifiedName` returns a sentinel-terminated
   slice so that backends that need null-termination do not need an
   additional copy.
 * Module.Union: implement a `getLayout` function which returns
   information about ABI size and alignment so that the LLVM backend can
   properly lower union types into llvm types.
 * Sema: `resolveType` now returns `error.GenericPoison` rather than a
   Type with tag `generic_poison`. Callsites that want to allow that
   need to bypass this higher-level function.
 * Sema: implement coercion of enums and enum literals to unions.
 * Sema: fix comptime mutation of pointers to unions
 * LLVM backend: fully implement proper lowering of union types and
   values according to the union layout, and update the handling of AIR
   instructions that deal with unions to support union layouts.
 * LLVM backend: handle `decl_ref_mut`
   - Maybe this should be unreachable since comptime vars should be
     changed to be non-mutable when they go out of scope, but it's
     harmless for the LLVM backend to support lowering the value.
 * Type: fix `requiresComptime` for optionals, pointers, and some other
   types. This function is still wrong for structs, unions, and enums.
2021-10-14 17:44:46 -07:00
Andrew Kelley
ed5a5e2293 move behavior tests that are passing for stage2 2021-10-13 21:43:19 -07:00
Andrew Kelley
0d4a94f32f stage2: improve handling of 0-bit types and arrays
* Make `alloc` AIR instructions call `resolveTypeLayout`.
 * `Sema.zirResolveInferredAlloc` now calls `requireRuntimeBlock` in the
   case that it operates on a non-comptime instruction.
 * `Type.abiSize` and `Type.abiAlignment` now return 0 for `void`
 * Sema: implement `resolveTypeFields` for unions.
 * LLVM Backend: support `ptr_elem_ptr` when the element type is 0-bit.
 * Type: improve `abiAlignment` implementation for structs to properly
   handle fields with non-default alignment.
 * Value: implement hashing array, vector, and structs.
2021-10-13 21:20:38 -07:00
Andrew Kelley
b0f80ef0d5 stage2: remove use of builtin.stage2_arch workaround
The LLVM backend no longer needs this hack! However, the other backends
still do. So there are still some traces of this workaround in use for now.
2021-10-13 18:43:43 -07:00
Andrew Kelley
df7d6d263e stage2: implement opaque declarations
* Module: implement opaque type namespace lookup
 * Add `Type.type` for convenience
 * Sema: fix `validateVarType` for pointer-to-opaque
 * x86_64 ABI: implement support for pointers
 * LLVM backend: fix lowering of opaque types
 * Type: implement equality checking for opaques
2021-10-13 17:53:28 -07:00
Andrew Kelley
da7fcfd158 stage2: implement Sema for elemVal for comptime slice 2021-10-13 16:31:07 -07:00
Andrew Kelley
e851d89113 Sema: implement comptime coerce_result_ptr and alloc
This is progress towards being able to use `builtin.cpu.arch` instead of
the `stage2_arch` workaround. The next blocker is comptime `elemVal`.
2021-10-13 14:16:01 -07:00
Andrew Kelley
a3104a4a78 stage2: fix comptime stores and sentinel-terminated arrays
* ZIR: the `array_type_sentinel` now has a source node attached to it
   for proper error reporting.
 * Refactor: move `Module.arrayType` to `Type.array`
 * Value: the `bytes` and `array` tags now include the sentinel, if the
   type has one. This simplifies comptime evaluation logic.
 * Sema: fix `zirStructInitEmpty` to properly handle when the type is
   void or a sentinel-terminated array. This handles the syntax `void{}`
   and `[0:X]T{}`.
 * Sema: fix the logic for reporting "cannot store runtime value in
   compile time variable" as well as for emitting a runtime store when a
   pointer value is comptime known but it is a global variable.
 * Sema: implement elemVal for double pointer to array. This can happen
   with this code for example: `var a: *[1]u8 = undefined; _ = a[0];`
 * Sema: Rework the `storePtrVal` function to properly handle nested
   structs and arrays.
   - Also it now handles comptime stores through a bitcasted pointer.
     When the pointer element type and the type according to the Decl
     don't match, the element value is bitcasted before storage.
2021-10-12 21:38:46 -07:00