19 Commits

Author SHA1 Message Date
xdBronch
4652729217 std.simd.suggestVectorSizeForCpu: fix missing argument in body 2023-05-13 13:35:50 +03:00
Linus Groh
94e30a756e std: fix a bunch of typos
The majority of these are in comments, some in doc comments which might
affect the generated documentation, and a few in parameter names -
nothing that should be breaking, however.
2023-04-30 18:16:04 -07:00
KOUNOIKE Yuusuke
5df31f3ef3
add wasm-simd support for suggestVectorSizeForCpu (#14992) 2023-03-20 17:45:12 +01:00
Andrew Kelley
aeaef8c0ff update std lib and compiler sources to new for loop syntax 2023-02-18 19:17:21 -07:00
Andrew Kelley
079f62881e std.simd.iota: make it always called at comptime
There's no reason for this to ever run at runtime; it should always be
used to generate a constant.
2023-01-04 18:37:53 -07:00
Andrew Kelley
5ca1753ff1 Revert "aarch64: reenable tests that are no longer regressed"
This reverts commit 3370d58956ecc744a004dff47b0437473f0ef7da.

This commit was done with an LLVM build that did not have assertions
enabled. There are LLVM assertions being triggered due to this commit.

Reopens #10627
Reopens #12013
Reopens #12027
2022-12-27 20:54:27 -07:00
r00ster91
3370d58956 aarch64: reenable tests that are no longer regressed
Closes #12013
Closes #10627
Closes #12027
2022-12-10 12:34:34 +01:00
Andrew Kelley
50eb7983cd remove most conditional compilation based on stage1
There are still a few occurrences of "stage1" in the standard library
and self-hosted compiler source, however, these instances need a bit
more careful inspection to ensure no breakage.
2022-12-06 20:38:54 -07:00
Ali Chraghi
ca27055cda all: rename @maximum to @max and @minimum to @min 2022-10-18 14:15:16 +03:00
Dan Ellis Echavarria
924679abc4
std.simd: change T to u16
The `element_bit_size` would break if `T` was signed due to `ceilPowerOfTwo` only working on unsigned numbers.
2022-09-07 15:22:30 +03:00
Dan Ellis Echavarria
d1d892c83c SIMD size suggestions: suggestions code now compiles, added more
architectures
The idea behind this is using the register capabilities in safe amounts,
 there is still some consideration to be done.
+ Fixed compile error using std.Target.<arch>.featureSetHas
+ X86 MMX and "3DNOW" 64 bits register usage considered for vector size
+ Added ARM Neon recommened usage of 128 bits (The size of the register)
+ Added AARCH64 Neon and SVE for 128 bits. SVE could use in theory up to
  2048 bits, but found only evidence of functional 512 bits on a super
       computer, decided on using 128 bits as a safety
+ Added Altivec recommendation of using the 128 bits long register
+ Using MIPS msa 2x64bits capabilities, usage of 64 bits registers for MDMX
  systems, need testing on how using bigger values affect performance
+ Using V extension on RISC-V, which is extendable via instructions, decided on 128 bits
  as a value to not use all registers
+ in SPARC the 64 bits registers are used, a max of 32 registers
  are to be used for configurable simd instructions, decided on using
the size of the register, need testing on performance hit on using a
bigger sized register vector size
2022-07-22 18:58:43 +03:00
Andrew Kelley
222ea6992d std: disable aarch64 tests that regressed from LLVM 14
See #12012
2022-07-06 15:57:36 -07:00
Andrew Kelley
cbdd21cd9a std: disable tests regressed from LLVM 14 2022-07-03 15:39:39 -07:00
Andrew Kelley
095e24e537 stage2: implement alignment calculation of vectors
closes #11856
2022-06-30 19:39:41 -07:00
Veikka Tuominen
413577c881 std: adjust for stage2 semantics 2022-06-07 21:27:07 +03:00
Damien Firmenich
5fafcc2b62
zig fmt: remove trailing whitespace on doc comments
Fixes #11353

The renderer treats comments and doc comments differently since doc
comments are parsed into the Ast. This commit adds a check after getting
the text for the doc comment and trims whitespace at the end before
rendering.

The `a = 0,` in the test is here to avoid a ParseError while parsing the
test.
2022-04-05 18:08:33 +03:00
ominitay
f654e16d06 std.simd: Fix suggestVectorSizeForCpu 2022-04-04 15:34:27 +03:00
Meghan
b73cf97c93
replace other uses of std.meta.Vector with @Vector (#11346) 2022-03-30 14:12:14 -04:00
tecanec
3beef3945c
std: SIMD utility functions
This file contains a collections of functions that may be useful for SIMD, such as generating a vector with a linear range of numbers starting at zero, joining two vectors together, getting the index of the first true in a vector of bools, etc.
2022-03-27 11:28:44 +03:00