326 Commits

Author SHA1 Message Date
William Sengir
c641fb8f05 stage2: fix {add,sub,mul}_with_overflow vectorization in LLVM backend 2022-05-16 13:55:26 -07:00
Koakuma
fb0692334e target: Rename sparcv9 -> sparc64
Rename all references of sparcv9 to sparc64, to make Zig align more with
other projects. Also, added new function to convert glibc arch name to Zig
arch name, since it refers to the architecture as sparcv9.

This is based on the suggestion by @kubkon in PR 11847.
(https://github.com/ziglang/zig/pull/11487#pullrequestreview-963761757)
2022-05-13 16:43:59 -04:00
Takeshi Yoneda
9654a54d4a Add Visibility field to ExportOptions.
Signed-off-by: Takeshi Yoneda <takeshi@tetrate.io>
2022-05-10 15:21:48 -07:00
Hannes Bredberg
ea3f5905f0 Add Win64 calling convention
Closes ziglang/zig#11585
2022-05-08 16:28:10 -04:00
Andrew Kelley
d136cd3202 LLVM: rework the previous commit
Idiomatic Zig, use const instead of var, simplify the logic.
2022-05-06 11:43:06 -07:00
Jakub Konka
edb3adaa33 stage2,llvm: handle softfloats in @intToFloat and @floatToInt
If the hw doesn't have support for exotic floating-point types such
as `f80`, we lower the call to a compiler-rt function call instead.

I've added a behavior test specifically targeting this use case which
now passes on `aarch64-macos`.

Additionally, this commit makes it possible to successfully build
stage3 on `aarch64-macos`. We can print the compiler's help message,
however, building with it needs a little bit more love still.
2022-05-05 22:29:30 -07:00
Andrew Kelley
44252f4d35 LLVM: fix C ABI for windows
* sret logic needed a check for hasRuntimeBits()
 * lower f128 on windows targets with the "sse" class rather than
   "memory". For reference, clang emits a compile error when __float128
   is used with the MSVC ABI, saying that this type is not supported.
   The docs for the x64 calling convention have both of these sentences:
   - "Any argument that doesn't fit in 8 bytes, or isn't 1, 2, 4, or 8 bytes,
     must be passed by reference."
   - "All floating point operations are done using the 16 XMM registers."
 * For i128, however, it is clear that the Windows calling convention
   wants such an object to be passed by reference. I fixed the LLVM
   lowering for function parameters to make this work.
2022-05-04 22:57:57 -07:00
Andrew Kelley
17fc44dd12 LLVM: fix x86_64 sysv C ABI for extern structs with sub-64 bit integers 2022-05-04 21:11:55 -07:00
Andrew Kelley
1b432b5576 stage2: implement global assembly
So far it's supported by the LLVM backend only. I recommend for the
other backends to wait for the resolution of #10761 before adding
support for this feature.
2022-05-04 20:38:53 -07:00
Andrew Kelley
259f784241 stage2: improve @sizeOf and @alignOf integers
Prior to this commit, the logic for ABI size and ABI alignment for
integers was naive and incorrect. This results in wasted hardware as
well as undefined behavior in the LLVM backend when we memset an
incorrect number of bytes to 0xaa due to disagreeing with LLVM about the
ABI size of integers.

This commit introduces a "max int align" value which is different per
Target. This value is used to derive the ABI size and alignment of all
integers.

This commit makes an interesting change from stage1, which treats
128-bit integers as 16-bytes aligned for x86_64-linux. stage1 is
incorrect. The maximum integer alignment on this system is only 8 bytes.
This change breaks the behavior test called "128-bit cmpxchg" because on
that target, 128-bit cmpxchg does require a 16-bytes aligned pointer to
a 128 bit integer. However, this alignment property does not belong on
*all* 128 bit integers - only on the pointer type in the `@cmpxchg`
builtin function prototype. The user can then use an alignment override
annotation on a 128-bit integer variable or struct field to obtain such
a pointer.
2022-05-04 17:34:16 -07:00
Andrew Kelley
ea7142c43f LLVM: set module PIC, PIE, and CodeModel
Some simple code from stage1 ported over to stage2.
2022-05-02 22:14:17 -07:00
Andrew Kelley
defda6202a LLVM: insert workaround for aarch64-windows f16 CodeView crash 2022-05-02 22:14:17 -07:00
Andrew Kelley
65389dc280 stage2: improve inline asm stage1 compatibility
* outputs can have names and be referenced with template replacements
   the same as inputs.
 * fix print_air.zig not decoding correctly.
 * LLVM backend: use a table for template names for simplicity
2022-05-02 22:14:17 -07:00
Andrew Kelley
09f1d62bdf add new builtin function @tan
The reason for having `@tan` is that we already have `@sin` and `@cos`
because some targets have machine code instructions for them, but in the
case that the implementation needs to go into compiler-rt, sin, cos, and
tan all share a common dependency which includes a table of data. To
avoid duplicating this table of data, we promote tan to become a builtin
alongside sin and cos.

ZIR: The tag enum is at capacity so this commit moves
`field_call_bind_named` to be `extended`. I measured this as one of
the least used tags in the zig codebase.

Fix libc math suffix for `f32` being wrong in both stage1 and stage2.
stage1: add missing libc prefix for float functions.
2022-04-27 16:45:23 -07:00
Andrew Kelley
087aedfa38 stage2: fix recent LLVM backend code
* std.math.snan: fix compilation error. Also make it and nan inline.
 * LLVM: use a proper enum type for float op instead of enum literal.
   Also various cleanups.
 * LLVM: use LLVMBuildVectorSplat for vector splat AIR instruction.
   - also the bindings had parameter order wrong
 * LLVM: additionally handle f16 lowering. For now all targets report OK
   but I think we will need to add some exceptions to this list.
2022-04-27 14:18:34 -07:00
Cody Tapscott
7d6a6ce87f stage2: Manually lower softfloat ops when needed
Updates stage2 to manually lower softfloat operations for all unary
floating point operations and arithmetic.

Softfloat support still needs to be added for conversion operators
(float<->float and int<->float)
2022-04-27 12:22:20 -07:00
Andrew Kelley
9c5fe5b5a4 LLVM: C calling convention lowering fixes
For parameters and return types of functions with the C calling
convention, the LLVM backend now has a special lowering for the function
type that makes the function adhere to the C ABI. The AIR instruction
lowerings for call, ret, and ret_load are adjusted to bitcast the real
type to the ABI type if necessary.

More work on this will need to be done, however, this improvement is
enough that stage3 now passes all the same behavior tests that stage2
passes - notably, translate-c no longer has a segfault due to C ABI
issues with Zig's Clang C API wrapper.
2022-04-21 20:27:06 -07:00
Andrew Kelley
f7596ae942 stage2: use indexes for Decl objects
Rather than allocating Decl objects with an Allocator, we instead allocate
them with a SegmentedList. This provides four advantages:
 * Stable memory so that one thread can access a Decl object while another
   thread allocates additional Decl objects from this list.
 * It allows us to use u32 indexes to reference Decl objects rather than
   pointers, saving memory in Type, Value, and dependency sets.
 * Using integers to reference Decl objects rather than pointers makes
   serialization trivial.
 * It provides a unique integer to be used for anonymous symbol names,
   avoiding multi-threaded contention on an atomic counter.
2022-04-20 17:37:35 -07:00
Andrew Kelley
a7c05c06be stage2: expose progress bar API to linker backends
This gives us insight as to what is happening when we are waiting for
things such as LLVM emit object and LLD linking.
2022-04-17 04:09:35 -07:00
Veikka Tuominen
101aac92c2 stage2: fix bugs preventing stage2 from building stage3 with LLVM 2022-04-15 23:32:26 +03:00
Veikka Tuominen
7be62f695f stage2 llvm: fix optional pointers to zero bit payloads 2022-04-15 19:17:50 +03:00
Veikka Tuominen
dbe0d3d579 stage2 llvm: handle dollar signs in asm template 2022-04-15 16:16:22 +03:00
Andrew Kelley
2587474717 stage2: progress towards stage3
* The `@bitCast` workaround is removed in favor of `@ptrCast` properly
   doing element casting for slice element types. This required an
   enhancement both to stage1 and stage2.
 * stage1 incorrectly accepts `.{}` instead of `{}`. stage2 code that
   abused this is fixed.
 * Make some parameters comptime to support functions in switch
   expressions (as opposed to making them function pointers).
 * Avoid relying on local temporaries being mutable.
 * Workarounds for when stage1 and stage2 disagree on function pointer
   types.
 * Workaround recursive formatting bug with a `@panic("TODO")`.
 * Remove unreachable `else` prongs for some inferred error sets.

All in effort towards #89.
2022-04-14 10:12:45 -07:00
Veikka Tuominen
83bb98e13b stage2 llvm: properly align error union payload 2022-04-02 19:31:32 -04:00
Veikka Tuominen
75c2cff40e stage2: handle assembly input names 2022-03-31 01:33:28 -04:00
Andrew Kelley
05947ea870 stage2: implement @intToError with safety
This commit introduces a new AIR instruction `cmp_lt_errors_len`. It's
specific to this use case for two reasons:

 * The total number of errors is not stable during semantic analysis; it
   can only be reliably checked when flush() is called. So the backend
   that is lowering the instruction must emit a relocation of some kind
   and then populate it during flush().
 * The fewer AIR instructions in memory, the better for compiler
   performance, so we squish complex meanings into AIR tags without
   hesitation.

The instruction is implemented only in the LLVM backend so far. It does
this by creating a simple function which is gutted and re-populated
with each flush().

AstGen now uses ResultLoc.coerced_ty for `@intToError` and Sema does the
coercion.
2022-03-29 22:19:06 -07:00
Andrew Kelley
f4a357d720 stage2: finish debug info for unions in the LLVM backend
Sema:

 * queue full resolution of std.builtin.Type.Error when doing `@typeInfo`
   for error sets.

LLVM backend:

 * change a TODO comment to a proper explanation of why debug info
   for structs is left as a fwd decl sometimes.
 * remove handling of packed unions which does not match the type
   information or constant generation code.
 * remove copy+pasted code
 * fix union debug info not matching the memory layout
 * remove unnecessary error checks and type casting
2022-03-28 16:27:45 -07:00
John Schmidt
c546608fca stage2: LLVM: (WIP) add union fields debug info 2022-03-28 16:24:51 -07:00
Veikka Tuominen
3c4ac47e00 stage2 llvm: fix union init of byRef values 2022-03-28 13:04:50 -07:00
Andrew Kelley
6d2ec7a4e3 LLVM: handle aggregate_init for packed structs 2022-03-27 14:22:47 -07:00
William Sengir
adc2824fa4
stage2: simplify scalar_ty for mul_add in LLVM backend 2022-03-26 16:29:48 -07:00
joachimschmidt557
9070ad7774
stage2 LLVM: Adjust to new AIR arithmetic overflow instructions 2022-03-26 17:21:42 +01:00
John Schmidt
f47db0a0db sema: use pl_op for @select 2022-03-25 16:13:54 +01:00
John Schmidt
12d5efcbe6 stage2: implement @select 2022-03-25 16:13:54 +01:00
Andrew Kelley
593130ce0a stage2: lazy @alignOf
Add a `target` parameter to every function that deals with Type and
Value.
2022-03-22 15:45:58 -07:00
William Sengir
4e357151a5 stage2: align store for vector-to-array bitcast in LLVM backend
This was causing a very rare segfault when LLVM would emit `vmovdqa`
using an unaligned memory operand on the stack.
2022-03-21 16:54:19 -07:00
William Sengir
961248cde3 stage2: make more instructions vector-compatible in LLVM backend 2022-03-21 16:54:19 -07:00
William Sengir
b96699059c stage2: implement cmp_vector for LLVM backend 2022-03-21 16:54:19 -07:00
William Sengir
0f48307041 stage2: add AIR instruction cmp_vector
The existing `cmp_*` instructions get their result type from `lhs`, but
vector comparison will always return a vector of bools with only the
length derived from its operands. This necessitates the creation of a
new AIR instruction.
2022-03-21 16:54:19 -07:00
Andrew Kelley
18a43b61f9
Merge pull request #11253 from Vexu/pretty-print-values
stage2: print values with types
2022-03-21 15:15:38 -04:00
Veikka Tuominen
0577069af5 stage2 llvm: fix lowerDeclRefValue for function aliases 2022-03-21 15:12:32 -04:00
Veikka Tuominen
a31fe0ff12 stage2: add way to print values with types 2022-03-21 15:03:42 +02:00
Veikka Tuominen
a8520fbd0f stage2: add dbg_block_{begin,end} instruction 2022-03-19 11:20:38 +02:00
John Schmidt
adfcc8851b Implement @byteSwap for vectors
Make the behavior tests for this a little more primitive to exercise as
little extra functionality as possible.
2022-03-17 18:00:48 -07:00
Andrew Kelley
7233a3324a stage2: implement @reduce
Notably, Value.eql and Value.hash are improved to treat NaN as equal to
itself, so that Type/Value can be hash map keys. Likewise float hashing
normalizes the float value before computing the hash.
2022-03-17 17:24:35 -07:00
Andrew Kelley
87779cfd93 stage2: prevent UB in the LLVM backend
* Sema: fix `zirTypeInfo` allocating with the wrong arenas for some
   stuff.
 * LLVM: split `airDbgInline` into two functions, one for each AIR tag.
   - remove the redundant copy to type_map_arena. This is the first
     thing that lowerDebugType does so this hack was probably just
     accidentally avoiding UB (which is still present prior to this
     commit).
   - don't store an inline fn inst into the di_map for the generic
     decl.
   - use a dummy function type for the debug info to avoid whatever UB
     is happening.
   - we are now ignoring the function type passed in with the
     dbg_inline_begin and dbg_inline_end.
 * behavior tests: prepare the vector tests to be enabled one at a time.

Mitigates #11199.
2022-03-17 00:00:41 -07:00
John Schmidt
c8ed813097 Implement @mulAdd for vectors 2022-03-16 20:11:05 -07:00
Andrew Kelley
d78b8c10b9 LLVM: fix slice debug info and functions
with return types that have no runtime bits
2022-03-16 17:22:16 -07:00
Andrew Kelley
1f313b3d7c LLVM: make the load function copy isByRef=true types 2022-03-16 11:52:22 -07:00
Veikka Tuominen
d83a26f068 stage2 llvm: keep track of inlined functions 2022-03-16 10:53:41 +02:00