17327 Commits

Author SHA1 Message Date
Veikka Tuominen
bf3c88b68d stage2: various fixes to get one test passing
* resolve error sets before merging them
* implement tupleFieldPtr
* make ret_ptr behave like alloc with zero sized types in llvm backend
2022-02-26 18:44:23 -05:00
Mitchell Hashimoto
156316bc7c
stage2: skip more tests for native backends 2022-02-26 13:56:50 -08:00
Joachim Schmidt
058e482247
Merge pull request #10996 from joachimschmidt557/stage2-arm
stage2 ARM: implement truncate to integers with <= 32 bits
2022-02-26 22:50:31 +01:00
Andrew Kelley
8349a644d0
Merge pull request #10986 from Vexu/stage2
stage2: actually coerce in coerce_result_ptr at comptime
2022-02-26 14:52:45 -05:00
Veikka Tuominen
bf5c055562 stage2: unify runtime and comptime coerce_result_ptr 2022-02-26 12:52:07 -07:00
Veikka Tuominen
bff7714a7c stage2: fix toAllocatedBytes on slices 2022-02-26 12:52:06 -07:00
Veikka Tuominen
ee149aaa03 stage2: actually coerce in coerce_result_ptr at comptime 2022-02-26 12:51:23 -07:00
Andrew Kelley
b3aa1ab693
Merge pull request #10994 from Vexu/typeof-scope
stage2: `@TypeOf` improvements
2022-02-26 14:47:43 -05:00
Mitchell Hashimoto
a5c9e8a494
typo in comment 2022-02-26 09:33:03 -08:00
Veikka Tuominen
315d4e8442 stage2: do not require function when evaluating typeOf
We only care about the instructions type; it will never actually be codegen'd.
2022-02-26 18:08:31 +02:00
Veikka Tuominen
ff72b8a819 stage2: evaluate TypeOf arguments in a separate scope 2022-02-26 18:08:11 +02:00
joachimschmidt557
f48f4baf67
stage2 ARM: generate correct variants of ldr instruction
When loading an i16 for example, generate ldrsh instead of ldrh
2022-02-26 13:00:01 +01:00
joachimschmidt557
8ef80cfaab
stage2 ARM: implement truncate to ints with bits <= 32 2022-02-26 12:59:57 +01:00
Al Hoang
db82c1b982 add constant for haiku
* re-enable zig build on haiku
2022-02-26 10:53:13 +02:00
Endel Dreyer
cd9a6fed4f fix typo on Thread's getHandle docs 2022-02-26 10:48:37 +02:00
Jakub Konka
0474943ddf
Merge pull request #10991 from ziglang/macho-pointer-rebase 2022-02-26 08:19:01 +01:00
Mitchell Hashimoto
f0232fc07d
stage2: split up the big sentinel peer cast test to multiple
This way we can fix them one at a time.
2022-02-25 18:56:27 -08:00
Mitchell Hashimoto
91af552f87
stage2: resolve peer types that trivially coerce 2022-02-25 18:47:10 -08:00
Mitchell Hashimoto
943ee59bb1
stage2: *[N]T to [*]T (and vice versa) 2022-02-25 17:29:50 -08:00
Mitchell Hashimoto
e442f88b76
stage2: add other backend skips until they determine they pass 2022-02-25 17:03:49 -08:00
Mitchell Hashimoto
4a6f918029
stage2: remove extranneous debug 2022-02-25 13:37:07 -08:00
Mitchell Hashimoto
bcf3eb5663
stage2: another passing test 2022-02-25 13:35:36 -08:00
Mitchell Hashimoto
1019181982
stage2: *[N]T and E![]T 2022-02-25 13:33:11 -08:00
Mitchell Hashimoto
117ef22d3c
stage2: peer resolve *[N]T to []T (and vice versa) 2022-02-25 13:21:07 -08:00
Jakub Konka
e0f5627d4a x64+aarch64: check for pointer to zero-bit type when lowering decl
Unless the pointer is a pointer to a function, if the pointee type
has zero-bits, we need to return `MCValue.none` as the `Decl` has
not been lowered to memory, and therefore, any GOT reference will be
wrong.
2022-02-25 21:59:19 +01:00
Jakub Konka
4b14384989 aarch64: check if type has runtime bits before allocating mem ptr 2022-02-25 21:59:19 +01:00
Jakub Konka
1b8ed7842c macho: redo selection of segment/section for decls and consts
* fix alignment issues for consts with natural ABI alignment not
  matching that of the `ldr` instruction in `aarch64` - solved by
  preceeding the `ldr` with an additional `add` instruction to form
  the full address before dereferencing the pointer.
* redo selection of segment/section for decls and consts based on
  combined type and value
2022-02-25 21:59:19 +01:00
Veikka Tuominen
bf6540ce50 Revert "stage2: make array len field type usize to match stage1"
This reverts commit 73bf418eb16a3e385218400cdc184f5d5e5aeaad.
2022-02-25 11:33:53 +02:00
Veikka Tuominen
73bf418eb1 stage2: make array len field type usize to match stage1
match stage1 behavior to avoid issues in standard library.
2022-02-25 11:25:56 +02:00
Luuk de Gram
0147eb9b58 wasm: Fix error union's size/alignment
Previously error unions were packed in memory. Now each 'field' is correctly
aligned to the error union's alignment.
2022-02-25 09:33:15 +01:00
Luuk de Gram
f4adb53bcf wasm: Refactor lowerUnnamedConst
Rather than ping ponging between codegen and the linker to generate the symbols/atoms
for a local constant and its relocations. We now create all neccesary objects within the linker.

This simplifies the code as we can now simply call `lowerUnnamedConst` from anywhere in codegen,
allowing us to further improve lowering constants into .rodata so we do not have to sacrifice
lowering certain types such as decl_ref's where its type is a slice.
2022-02-25 09:33:15 +01:00
Andrew Kelley
27eb42c15e Sema: implement tupleFieldVal, fix comptime elem_ptr 2022-02-24 22:28:37 -07:00
Andrew Kelley
adb746a701 stage2: improved handling of store_to_block_ptr
* AstGen: remove the setBlockBodyEliding function. This is no longer
   needed after 63788b2a511eb87974065a052e2436b0c6202544.
 * Sema: store_to_block_ptr instruction is handled as
   store_to_inferred_ptr or store, as necessary.
2022-02-24 22:28:37 -07:00
protty
5d30e8016d
time: introduce Instant (#10972) 2022-02-24 18:51:44 -05:00
Veikka Tuominen
63788b2a51 stage2: change how stale store_to_block_ptrs are detected
Instead of explicitly setting lhs to .none,
check if the lhs instruction was analyzed.
This simpler approach also handles stores from nested blocks correctly.
2022-02-24 18:32:08 -05:00
Isaac Freund
52a2aa11e2 std: work around current packed struct situation
As of 6249a24, align() is not allowed on packed struct fields
and as such the align(4) was removed from the first field of
EdidOverrideProtocolAttributes. The endgame here is packed struct
backed by explicit integers, in this case a u32, but until that
is implemented put the align(4) on the pointer to avoid breaking
someone's UEFI code in a hard to debug way.
2022-02-24 16:08:37 -05:00
Andrew Kelley
e06cb31659
Merge pull request #10982 from Vexu/stage2
stage2: implement fieldParentPtr
2022-02-24 15:52:56 -05:00
Andrew Kelley
5ab5e2e673 Revert "Merge pull request #10950 from hexops/sg/responsefiles"
This reverts commit 136a43934bc08dc3aee85f1182904b97456601d3, reversing
changes made to 9dd839b7ed15d1191f3303d069cffe0473e03e83.

This broke the behavior of `zig run`.
2022-02-24 12:11:11 -07:00
Veikka Tuominen
cbd5d6c704 spirv spec: do not align packed struct fields 2022-02-24 19:48:34 +02:00
Veikka Tuominen
b034c45b2b stage2: implement fieldParentPtr 2022-02-24 19:48:34 +02:00
Andrew Kelley
6249a24e81 stage2: integer-backed packed structs
This implements #10113 for the self-hosted compiler only. It removes the
ability to override alignment of packed struct fields, and removes the
ability to put pointers and arrays inside packed structs.

After this commit, nearly all the behavior tests pass for the stage2 llvm
backend that involve packed structs.

I didn't implement the compile errors or compile error tests yet. I'm
waiting until we have stage2 building itself and then I want to rework
the compile error test harness with inspiration from Vexu's arocc test
harness. At that point it should be a much nicer dev experience to work
on compile errors.
2022-02-23 23:59:25 -07:00
Mitchell Hashimoto
65c0475970 stage2: peer type resolution *[N]T and *[M]T to []const T 2022-02-24 08:50:26 +02:00
Jakub Konka
ffb7ac6755 elf: use fully qualified decl names in the linker 2022-02-24 00:01:11 +01:00
Jakub Konka
9d098318e2
Merge pull request #10977 from joachimschmidt557/stage2-aarch64
stage2 AArch64: more support for PIE targets (Mach-O)
2022-02-24 00:00:15 +01:00
Jakub Konka
136a43934b
Merge pull request #10950 from hexops/sg/responsefiles
Do not fail to build if 'zig build-lib' etc. arguments exceed OS limits
2022-02-23 22:54:25 +01:00
Jakub Konka
9dd839b7ed
Merge pull request #10976 from ziglang/x64-macos-fixes
x64: print test runner results on macos
2022-02-23 22:40:06 +01:00
Jan Philipp Hafer
5d89955543 compiler_rt: specify goals, organize README and compiler_rt.zig
* goals
  - zig as linker for object files generated by other compilers
  - zig-specific runtime features for eventual standardisation

* changes
  - missing routines are marked with `missing`
  - structure inspired by libgcc docs, but improved order and wording
  - rename misspelled functions
  - reorder and rephrase compiler_rt.zig to reflect documentation
  - potential decimal float or fixed-point arithmetic support:
    * 'Decimal float library routines' ca. 120 functions
    * 'Fixed-point fractional library routines' ca. 300 functions

thanks to @Vexu for multiple reviews and @scheibo for review
2022-02-23 16:38:51 -05:00
Andrew Kelley
ecf56d85ef
Merge pull request #10969 from Vexu/stage2
stage2: fn typeinfo params
2022-02-23 16:10:17 -05:00
joachimschmidt557
f91fe9afb9
stage2 AArch64: more support for MCValue.got_load and direct_load 2022-02-23 21:58:13 +01:00
joachimschmidt557
4683f94463
stage2 AArch64: remove MIR load_memory instruction
This instruction now just represents loading from a hard-coded adrress
after extracting the other use cases for load_memory into load_got and
load_direct.
2022-02-23 21:57:59 +01:00