87 Commits

Author SHA1 Message Date
Andrew Kelley
7630a5c566 stage2: more progress towards Module/astgen building with new mem layout 2021-02-12 23:47:17 -07:00
Jonathan Marler
1480c42806 require specifier for arrayish types 2021-02-09 22:25:52 -08:00
joachimschmidt557
6a5a6386c6 stage2 ARM: fix register allocation in genArmBinOp
Previously, this would reuse an operand even if reuseOperand returned
false for both operands.

genArmBinOpCode was also changed to be more Three-address code oriented
in the process.
2021-02-09 23:58:41 +01:00
joachimschmidt557
446ebddb93 stage2 ARM: save function arguments to stack for debugging
This changes genArg to copy registers to the stack for better
debugging. Thus, it requires genSetStack to be implemented in order for
genArg to work.
2021-02-01 12:17:24 -08:00
Andrew Kelley
6c8985fcee astgen: rework labeled blocks 2021-01-31 21:09:22 -07:00
Andrew Kelley
588171c30b sema: after block gets peer type resolved, insert type coercions
on the break instruction operands. This involves a new TZIR instruction,
br_block_flat, which represents a break instruction where the operand is
the result of a flat block. See the doc comments on the instructions for
more details.

How it works: when adding break instructions in semantic analysis, the
underlying allocation is slightly padded so that it is the size of a
br_block_flat instruction, which allows the break instruction to later
be converted without removing instructions inside the parent body. The
extra type coercion instructions go into the body of the br_block_flat,
and backends are responsible for dispatching the instruction correctly
(it should map to the same function calls for related instructions).
2021-01-31 21:09:22 -07:00
Andrew Kelley
b7452fe35f stage2: rework astgen result locations
Motivating test case:

```zig
export fn _start() noreturn {
    var x: u64 = 1;
    var y: u32 = 2;
    var thing: u32 = 1;
    const result = if (thing == 1) x else y;
    exit();
}
```

The main idea here is for astgen to output ideal ZIR depending on
whether or not the sub-expressions of a block consume the result
location. Here, neither `x` nor `y` consume the result location of the
conditional expression block, and so the ZIR should communicate the
result of the condbr using break instructions, not with the result
location pointer.

With this commit, this is accomplished:

```
  %22 = alloc_inferred()
  %23 = block({
    %24 = const(TypedValue{ .ty = type, .val = bool})
    %25 = deref(%18)
    %26 = const(TypedValue{ .ty = comptime_int, .val = 1})
    %27 = cmp_eq(%25, %26)
    %28 = as(%24, %27)
    %29 = condbr(%28, {
      %30 = deref(%4)
      < there is no longer a store instruction here >
      %31 = break("label_23", %30)
    }, {
      %32 = deref(%11)
      < there is no longer a store instruction here >
      %33 = break("label_23", %32)
    })
  })
  %34 = store_to_inferred_ptr(%22, %23) <-- the store is only here
  %35 = resolve_inferred_alloc(%22)
```

However if the result location gets consumed, the break instructions
change to break_void, and the result value is communicated only by the
stores, not by the break instructions.

Implementation:

 * The GenZIR scope that conditional branches uses now has an optional
   result location pointer field and a count of how many times the
   result location ended up being an rvalue (not consumed).
 * When rvalue() is called on a result location for a block, it
   increments this counter. After generating the branches of a block,
   astgen for the conditional branch checks this count and if it is 2
   then the store_to_block_ptr instructions are elided and it calls
   rvalue() using the block result (which will account for peer type
   resolution on the break operands).

astgen has many functions disabled until they can be reworked with these
new semantics. That will be done before merging the branch.

There are some new rules for astgen to follow regarding result locations
and what you are allowed/required to do depending on which one is passed
to expr(). See the updated doc comments of ResultLoc for details.

I also changed naming conventions of stuff in this commit, sorry about
that.
2021-01-31 21:09:22 -07:00
Andrew Kelley
ecc246efa2 stage2: rework ZIR/TZIR for optionals and error unions
* fix wrong pointer const-ness when unwrapping optionals
 * allow grouped expressions and orelse as lvalues
 * ZIR for unwrapping optionals: no redundant deref
   - add notes to please don't use rlWrapPtr, this function should be
     deleted
 * catch and orelse: better ZIR for non-lvalue: no redundant deref;
   operate entirely on values. lvalue case still works properly.
   - properly propagate the result location into the target expression
 * Test harness: better output when tests fail due to compile errors.
 * TZIR: add instruction variants. These allow fewer TZIR instructions to
   be emitted from zir_sema. See the commit diff for per-instruction
   documentation.
   - is_null
   - is_non_null
   - is_null_ptr
   - is_non_null_ptr
   - is_err
   - is_err_ptr
   - optional_payload
   - optional_payload_ptr
 * TZIR: removed old naming convention instructions:
   - isnonnull
   - isnull
   - iserr
   - unwrap_optional
 * ZIR: add instruction variants. These allow fewer ZIR instructions to
   be emitted from astgen. See the commit diff for per-instruction
   documentation.
   - is_non_null
   - is_null
   - is_non_null_ptr
   - is_null_ptr
   - is_err
   - is_err_ptr
   - optional_payload_safe
   - optional_payload_unsafe
   - optional_payload_safe_ptr
   - optional_payload_unsafe_ptr
   - err_union_payload_safe
   - err_union_payload_unsafe
   - err_union_payload_safe_ptr
   - err_union_payload_unsafe_ptr
   - err_union_code
   - err_union_code_ptr
 * ZIR: removed old naming convention instructions:
   - isnonnull
   - isnull
   - iserr
   - unwrap_optional_safe
   - unwrap_optional_unsafe
   - unwrap_err_safe
   - unwrap_err_unsafe
   - unwrap_err_code
2021-01-18 19:29:18 -07:00
joachimschmidt557
6c7e66613d stage2 AArch64: implement jump 2021-01-18 22:22:53 +01:00
Jakub Konka
61b8d42d5c
Merge pull request #7808 from joachimschmidt557/stage2-aarch64
Stage2 AArch64: Fix genSetStack
2021-01-18 20:01:44 +01:00
joachimschmidt557
458011f21f
stage2 AArch64: update function prologue and epilogue to include stack
offsets
2021-01-17 23:12:04 +01:00
joachimschmidt557
c6cb02c226
stage2 AArch64: fix stack offsets in genSetStack 2021-01-17 22:22:47 +01:00
Jakub Konka
8118336585 macho: refactor undef symbol handling
Now, we don't erroneously write to the string table on every
write of global and undef symbols.
2021-01-17 21:01:52 +01:00
Jakub Konka
b25cf7db02 stage2 aarch64: add basic function pro/epilogue
Fix typo in `nop` implementation.
Simplify `aarch64` macOS tests.
2021-01-17 14:57:53 +01:00
Jakub Konka
e292f33de7 stage2 aarch64: add basic genSetStack 2021-01-17 14:57:36 +01:00
Andrew Kelley
8c9ac4db97 stage2: implement error notes and regress -femit-zir
* Implement error notes
   - note: other symbol exported here
   - note: previous else prong is here
   - note: previous '_' prong is here
 * Add Compilation.CObject.ErrorMsg. This object properly converts to
   AllErrors.Message when the time comes.
 * Add Compilation.CObject.failure_retryable. Properly handles
   out-of-memory and other transient failures.
 * Introduce Module.SrcLoc which has not only a byte offset but also
   references the file which the byte offset applies to.
 * Scope.Block now contains both a pointer to the "owner" Decl and the
   "source" Decl. As an example, during inline function call, the
   "owner" will be the Decl of the caller and the "source" will be the
   Decl of the callee.
 * Module.ErrorMsg now sports a `file_scope` field so that notes can
   refer to source locations in a file other than the parent error
   message.
 * Some instances where a `*Scope` was stored, now store a
   `*Scope.Container`.
 * Some methods in the `Scope` namespace were moved to the more specific
   type, since there was only an implementation for one particular tag.
   - `removeDecl` moved to `Scope.Container`
   - `destroy` moved to `Scope.File`
 * Two kinds of Scope deleted:
   - zir_module
   - decl
 * astgen: properly use DeclVal / DeclRef. DeclVal was incorrectly
   changed to be a reference; this commit fixes it. Fewer ZIR
   instructions processed as a result.
   - declval_in_module is renamed to declval
   - previous declval ZIR instruction is deleted; it was only for .zir
     files.
 * Test harness: friendlier diagnostics when an unexpected set of errors
   is encountered.
 * zir_sema: fix analyzeInstBlockFlat by properly calling resolvingInst
   on the last zir instruction in the block.

Compile log implementation:
 * Write to a buffer rather than directly to stderr.
 * Only keep track of 1 callsite per Decl.
 * No longer mutate the ZIR Inst struct data.
 * "Compile log statement found" errors are only emitted when there are
   no other compile errors.

-femit-zir and support for .zir source files is regressed. If we wanted
to support this again, outputting .zir would need to be done as yet
another backend rather than in the haphazard way it was previously
implemented.

For parsing .zir, it was implemented previously in a way that was not
helpful for debugging. We need tighter integration with the test harness
for it to be useful; so clearly a rewrite is needed. Given that a
rewrite is needed, and it was getting in the way of progress and
organization of the rest of stage2, I regressed the feature.
2021-01-16 22:51:01 -07:00
joachimschmidt557
d2a297c2b3 stage2 ARM: add extra load/store instructions 2021-01-16 12:06:31 -08:00
joachimschmidt557
fbd5fbe729 stage2 AArch64: add very basic return values 2021-01-16 12:05:38 -08:00
Jakub Konka
f0d7ec6f33 macho: add x86_64 support 2021-01-13 23:55:37 +01:00
Jakub Konka
7d40aaad2b macho: document more code + add test case 2021-01-13 23:55:18 +01:00
Jakub Konka
b86d0e488b macho: refactor writing and managing externs 2021-01-13 23:55:06 +01:00
Jakub Konka
44a052a65f macho: write out stubs for new externs only 2021-01-13 23:54:46 +01:00
Jakub Konka
f44732c1b0 macho: populate stubs and stub_helper 2021-01-13 23:53:46 +01:00
Jakub Konka
5487dd13ea stage2: lay the groundwork in prep for extern fn
This commit lays the groundwork in preparation for implementing
handling of extern functions in various backends.
2021-01-13 14:51:23 -08:00
joachimschmidt557
a7da90071e stage2: fix bug in genArg
When an argument is unused in the function body, still increment
arg_index so we still select the correct arguments in the args slice.
2021-01-10 00:41:02 -08:00
Andrew Kelley
d7d905696c
Merge pull request #7622 from tetsuo-cpp/array-hash-map-improvements
std: Support equivalent ArrayList operations in ArrayHashMap
2021-01-06 16:32:23 -08:00
joachimschmidt557
be6ac82ee1 stage2 ARM: fix stack offsets for genSetReg and genSetStack 2021-01-06 15:53:10 -08:00
joachimschmidt557
480d6182ad stage2 ARM: fix offsets in exitlude jump relocations 2021-01-06 15:53:10 -08:00
Alex Cameron
d92ea56884 std: Support equivalent ArrayList operations in ArrayHashMap 2021-01-06 00:55:51 +11:00
joachimschmidt557
aa0906e9aa stage2 x86_64: fix bug in Function.gen
Previously, the x86_64 backend would remove code for exitlude relocs
if the jump amount were 0. This causes issues as earlier jumps rely on
the jump being present at the same address.
2021-01-03 19:54:12 -08:00
Jakub Konka
2a410baa2b stage2: implement basic function params aarch64
Implement missing `.register` prong for `aarch64` `genSetReg`.
2021-01-03 23:03:20 +01:00
Andrew Kelley
006e7f6805 stage2: re-use ZIR for comptime and inline calls
Instead of freeing ZIR after semantic analysis, we keep it around so
that it can be used for comptime calls, inline calls, and generic
function calls. ZIR memory is now managed by the Decl arena.

Debug dump() functions are conditionally compiled; only available in
Debug builds of the compiler.

Add a test for an inline function call.
2021-01-02 19:11:55 -07:00
Andrew Kelley
9362f382ab stage2: implement function call inlining in the frontend
* remove the -Ddump-zir thing. that's handled through --verbose-ir
 * rework Fn to have an is_inline flag without requiring any more memory
   on the heap per function.
 * implement a rough first version of dumping typed zir (tzir) which is
   a lot more helpful for debugging than what we had before. We don't
   have a way to parse it though.
 * keep track of whether the inline-ness of a function changes because
   if it does we have to go update callsites.
 * add compile error for inline and export used together.

inline function calls and comptime function calls are implemented the
same way. A block instruction is set up to capture the result, and then
a scope is set up that has a flag for is_comptime and some state if the
scope is being inlined.

when analyzing `ret` instructions, zig looks for inlining state in the
scope, and if found, treats `ret` as a `break` instruction instead, with
the target block being the one set up at the inline callsite.

Follow-up items:
 * Complete out the debug TZIR dumping code.
 * Don't redundantly generate ZIR for each inline/comptime function
   call. Instead we should add a new state enum tag to Fn.
 * comptime and inlining branch quotas.
 * Add more test cases.
2021-01-02 19:11:19 -07:00
LemonBoy
1c13ca5a05 stage2: Use {s} instead of {} when formatting strings 2021-01-02 17:12:57 -07:00
joachimschmidt557
c5ec096b2f stage2 AArch64: add logical (shifted register) instructions 2021-01-01 14:43:12 -08:00
joachimschmidt557
c52ca0b178
stage2 ARM: implement genSetReg with compare_flags 2021-01-01 12:22:16 +01:00
joachimschmidt557
85e1b47c40
stage2 ARM: implement genCondBr for compare_flags 2021-01-01 12:22:16 +01:00
joachimschmidt557
4d2919a1ee
stage2 ARM: implement genCondBr 2021-01-01 12:22:14 +01:00
Andrew Kelley
3f7d9b5fc1 stage2: rework Value Payload layout
This is the same as the previous commit but for Value instead of Type.

Add `Value.castTag` and note that it is preferable to call than
`Value.cast`. This matches other abstractions in the codebase.

Added a convenience function `Value.Tag.create` which really cleans up
the callsites of creating `Value` objects.

`Value` tags can now share payload types. This is in preparation for
another improvement that I want to do.
2020-12-30 21:41:02 -08:00
Andrew Kelley
133da8692e stage2: rework Type Payload layout
Add `Type.castTag` and note that it is preferable to call than
`Type.cast`. This matches other abstractions in the codebase.

Added a convenience function `Type.Tag.create` which really cleans up
the callsites of creating `Type` objects.

`Type` payloads can now share types. This is in preparation for another
improvement that I want to do.
2020-12-30 21:41:02 -08:00
joachimschmidt557
82236a5029
stage2 ARM: implement basic binary bitwise operations 2020-12-21 19:24:21 +01:00
Jakub Konka
2082c27557 stage2+aarch64: clean up offset helper structs 2020-12-09 17:21:21 +01:00
Jakub Konka
e91dbab256 stage2+aarch64: fix stage2 tests 2020-12-09 17:21:17 +01:00
Jakub Konka
eca0727417 stage2+aarch64: use stp and ldp to navigate MachO jump table 2020-12-09 17:20:58 +01:00
Andrew Kelley
ecf7dfcd3a
Merge pull request #7273 from kubkon/lld-codesig-poc
lld+macho: patch lld output on Apple Silicon by calculating and embedding adhoc code signature
2020-12-03 13:41:31 -08:00
Andrew Kelley
463186e856 stage2: wire up -Dskip-non-native
The purpose of this is to save time in the edit-compile-test cycle when
working on stage2 code.
2020-12-02 14:52:56 -07:00
Jakub Konka
1f7fb560ab lld: use commands.LoadCommand in self-hosted linker 2020-12-01 10:49:31 +01:00
joachimschmidt557
2ad2636588
stage2 ARM: use strb + implement genBoolOp 2020-11-28 18:19:22 +01:00
joachimschmidt557
f06f0ebcda
stage2 ARM: Implement genNot 2020-11-28 18:19:22 +01:00
joachimschmidt557
85a3991a43
stage2 codegen: use switch in genBoolOp 2020-11-28 18:19:22 +01:00