1040 Commits

Author SHA1 Message Date
Andrew Kelley
ba6e5cbfd2 stage2: add the .debug_line header and associated data types
* the .debug_line header is written properly
 * link.File.Elf gains:
   - SrcFn, which is now a field in Module.Fn
   - SrcFile, which is now a field in Module.Scope.File
 * link.File.Elf gets a whole *Package field rather than only
   root_src_dir_path.
 * the fields first_dbg_line_file and last_dbg_line_file tell where the
   Line Number Program begins and ends, which alows moving files when
   the header gets too big, and allows appending files to the end.
 * codegen is passed a buffer for emitting .debug_line
   Line Number Program opcodes for functions.

See #5963

There is some work-in-progress code here, but I need to go make some
experimental changes to changing how to represent source locations and I
want to do that in a separate commit.
2020-08-02 12:02:43 -07:00
Isaac Freund
6123201f06 stage2: move format-specific code to link.File.X
This makes the code outside of link.File.Elf less elf-specific and will
allow for easier implementation of other formats such as wasm.
2020-08-02 18:07:10 +00:00
Andrew Kelley
0962cc5a32 stage2: implement .debug_aranges DWARF 2020-07-31 01:16:34 -07:00
Andrew Kelley
acd0dabab2 stage2: add some tracy calls to link.zig functions 2020-07-30 23:51:14 -07:00
Andrew Kelley
f1c1b8c02d stage2: add DWARF info for the main compilation unit 2020-07-31 06:48:17 +00:00
Vexu
1f8f434b9c
compiler_rt: add floatditf 2020-07-29 18:03:44 +03:00
Andrew Kelley
8899e6e334 stage2: codegen: fix off-by-one stack variable offsets 2020-07-29 02:29:37 -07:00
Andrew Kelley
606f157a6b stage2: register-aliasing-aware codegen
* unify duplicated register allocation codepath
 * support the x86_64 concept of register aliasing
 * slightly improved memset codegen, supports sizes 1, 2, 4, 8
2020-07-29 02:29:37 -07:00
Andrew Kelley
1bbfa36b76 stage2: improved codegen
* multiple returns jump to one canonical function exitlude. This is in
   preparation for the defer feature.
 * simple elision of trivial jump relocs.
 * omit prelude/exitlude for naked calling convention functions.
 * fix not switching on arch for prelude/exitlude
 * fix swapped registers when setting stack mem from a register
2020-07-29 02:29:37 -07:00
Andrew Kelley
64a1a280ef stage2: fix superfluous returnvoid ZIR 2020-07-29 02:29:37 -07:00
Andrew Kelley
4beff80b2f stage2: codegen handles undefined values
* `optimize_mode` is passed to `link.File` and stored there
 * improve the debugging function `Module.dumpInst`
 * get rid of `Value.the_one_possible_value` in favor of a few more
   specific values for different types. This is less buggy, one less
   footgun.
 * `Type.onePossibleValue` now returns a `?Value` instead of `bool`.
 * codegen handles undefined values. `undef` is a new `MCValue` tag.
   It uses 0xaa values depending on optimization mode. However
   optimization mode does not yet support scope overrides.
 * link.zig: move the `Options` field from `File.Elf` and `File.C` to
   the base struct.
   - fix the Tag enum to adhere to style conventions
 * ZIR now supports emitting undefined values.
 * Fix the logic of comptime math to properly compare against zero using
   the `compareWithZero` function.
2020-07-29 02:29:37 -07:00
Andrew Kelley
2b8e7deeda stage2: add ZIR emitType support for simple pointer types 2020-07-29 02:29:37 -07:00
Andrew Kelley
99d2d9bf64 stage2: fix format() of mutable pointer types 2020-07-29 02:29:37 -07:00
Andrew Kelley
cb3e8e323d stage2: x86_64 codegen for movs to/from stack variables 2020-07-29 02:29:37 -07:00
Andrew Kelley
5ccee4c986 stage2: more progress towards mutable local variables
* implement sema for runtime deref, store pointer, coerce_to_ptr_elem,
   and store
 * identifiers support being lvalues, except for decls is still TODO
 * codegen supports load, store, ref, alloc
 * introduce more MCValue union tags to support pointers
 * add load, ref, store typed IR instructions
 * add Type.isVolatilePtr
2020-07-29 02:29:36 -07:00
Andrew Kelley
d726c2a2d3 self-hosted: beginnings of stack allocation
Comment out non-x86_64 architectures for now in codegen.zig, because
they all have compile errors for their codepaths anyway, and it was
bloating the compilation speed and memory usage when stage1 tried to
build self-hosted. Here's the panic message:

"Backend architectures that don't have good support yet are commented
out, to improve compilation performance. If you are interested in one
of these other backends feel free to uncomment them. Eventually these
will be completed, but stage1 is slow and a memory hog."

This is a workaround to lower the time it takes to build self-hosted
with stage1 as well as use less memory. It should fix the CI.

Additionally:
 * Add `single_mut_pointer` support to `Type`
 * Trivial implementation of stack allocation in codegen.zig. It does
   not deal with freeing yet, and it's missing the stack pointer
   adjustment prologue.
 * Add the `alloc` IR instruction and semantic analysis for `alloc` ZIR
   instruction.
2020-07-28 01:43:04 -07:00
Andrew Kelley
0965724e31 self-hosted: refactor some code out of Module.zig into zir_sema.zig
This makes sense from an organizational point of view, as explained by
this new doc comment at the top of the new file:

//! Semantic analysis of ZIR instructions.
//! This file operates on a `Module` instance, transforming untyped ZIR
//! instructions into semantically-analyzed IR instructions. It does type
//! checking, comptime control flow, and safety-check generation. This is the
//! the heart of the Zig compiler.
//! When deciding if something goes into this file or into Module, here is a
//! guiding principle: if it has to do with (untyped) ZIR instructions, it goes
//! here. If the analysis operates on typed IR instructions, it goes in Module.

Before:
   4009 src-self-hosted/Module.zig

After:
   2776 src-self-hosted/Module.zig
   1128 src-self-hosted/zir_sema.zig

This should be sufficient to avoid the situation we have in stage1 where
ir.cpp is 32,516 lines.
2020-07-27 22:44:18 -07:00
Andrew Kelley
b8e22d2002 stage2: implement integer return values 2020-07-27 18:59:13 -07:00
Andrew Kelley
3e0a46281c stage2: fix function calls always having void return type 2020-07-27 18:59:13 -07:00
Andrew Kelley
488df7f1d1 stage2: astgen for all arithmetic and assignments 2020-07-27 17:09:47 -07:00
Vexu
e7007fa7bd
translate-c: use ArrayList for macro tokens 2020-07-27 15:38:56 +03:00
Henrik Laxhuber
9f6401c692 Fix a use of appendToken to appendIdentifier in translate-c 2020-07-27 13:43:49 +03:00
Henrik Laxhuber
442025481c Fix parsing of unsigned in translate-c.
Previously, `unsigned` was parsed as the shorthand for `unsigned int`.
This commit introduces code to parse `unsigned short`, `unsigned int`,
`unsigned long`, and `unsigned long long`.

There is a comment in the code about std.c.parse` - Im not
familiar with zig internals, but it seems like this is a separate
C parsing implementation. In the long run, it probably makes
sense to merge both implementations, so this commit should be
regarded as a quick fix that doesn't address an apparently
underlying issue.
2020-07-27 13:43:49 +03:00
Andrew Kelley
09b0ad494b stage2: remove superfluous else => unreachable 2020-07-25 23:32:30 -07:00
Andrew Kelley
a36772ee64
Merge pull request #5693 from antlilja/switch-unreachable-else
Add error message for unreachable else prong in switch
2020-07-26 05:46:18 +00:00
Michael Dusan
3b26e50863 macOS: macho ld64.lld fixes
* bring `construct_linker_job_macho` to parity with
   `construct_linker_job_elf`
 * macho now sets `-error-limit`
 * macho on macOS now sets `-macosx_version_min` and `-sdk_version`
   to `10.13` when running `zig0`
 * macho now detects when `-l` prefix is not needed
 * macho on macOS detects system libraries in a case-insensitive manner
 * macho now ads user-specified libraries to linker command-line args
   when condition `is_native_os != true`
 * re-ordered some macho args positions to match elf positions

closes #5059
closes #5067
2020-07-24 20:01:18 +00:00
Luuk de Gram
3019ab9391
Fix resolvepeertype() int signess and feedback improvements 2020-07-24 17:51:24 +02:00
Luuk de Gram
470264a4f5
Restructuring and f32/f64 support 2020-07-24 17:16:48 +02:00
Luuk de Gram
97e92d868e
Rebase and skeleton for float support 2020-07-24 17:16:48 +02:00
Luuk de Gram
ee7fbb9548
Restructured arithmetic operations 2020-07-24 17:16:48 +02:00
Andrew Kelley
aac6e8c418 self-hosted: AST flattening, astgen improvements, result locations, and more
* AST: flatten ControlFlowExpression into Continue, Break, and Return.
 * AST: unify identifiers and literals into the same AST type: OneToken
 * AST: ControlFlowExpression uses TrailerFlags to optimize storage
   space.
 * astgen: support `var` as well as `const` locals, and support
   explicitly typed locals. Corresponding Module and codegen code is not
   implemented yet.
 * astgen: support result locations.
 * ZIR: add the following instructions (see the corresponding doc
   comments for explanations of semantics):
   - alloc
   - alloc_inferred
   - bitcast_result_ptr
   - coerce_result_block_ptr
   - coerce_result_ptr
   - coerce_to_ptr_elem
   - ensure_result_used
   - ensure_result_non_error
   - ret_ptr
   - ret_type
   - store
   - param_type
 * the skeleton structure for result locations is set up. It's looking
   pretty clean so far.
 * add compile error for unused result and compile error for discarding
   errors.
 * astgen: split builtin calls up to implemented manually, and implement
   `@as`, `@bitCast` (and others) with respect to result locations.
 * add CLI support for hex and raw object formats. They are not
   supported by the self-hosted compiler yet, and emit errors.
 * rename `--c` CLI to `-ofmt=[objectformat]` which can be any of the
   object formats. Only ELF and C are supported so far. Also added missing
   help to the help text.
 * Remove hard tabs from C backend test cases. Shame on you Noam, you
   are grounded, you should know better, etc. Bad boy.
 * Delete C backend code and test case that relied on comptime_int
   incorrectly making it all the way to codegen.
2020-07-23 23:05:26 -07:00
Vexu
dd89297388
stage2: actually implement float casting 2020-07-21 22:34:14 +03:00
Vexu
c29c79b17a
stage2: remove some dead code, fix build on aarch64 2020-07-21 22:34:14 +03:00
Vexu
7e7d1df4da
stage2: add floatCast to zir and ir 2020-07-21 22:34:12 +03:00
Vexu
7b52dbbf83
stage2: implement some casts for numbers 2020-07-21 22:29:29 +03:00
Vexu
da217fadeb
stage2: astgen for floats and other primitive literals 2020-07-21 22:29:28 +03:00
Vexu
e77ca6af70
stage2: add float values 2020-07-21 22:29:28 +03:00
Andrew Kelley
8ee629aa4c stage2: ability for ZIR to map multiple tags to the same type 2020-07-21 12:13:15 -07:00
Andrew Kelley
7a1a924788 stage2: AST: (breaking) flatten out suffix operations 2020-07-21 10:52:24 -07:00
Andrew Kelley
1ac28eed83 stage2 AST: rename OptionalUnwrap to OrElse
preparing to flatten suffix operations AST
2020-07-21 10:46:47 -07:00
Andrew Kelley
1cfe43d563
Merge pull request #5888 from pfgithub/stage-2-testing-Copy
stage2: period and suffixop
2020-07-21 17:42:46 +00:00
Andrew Kelley
ef91b11295 stage2: register allocator processes operand deaths
also rework the IR data structures
2020-07-20 13:12:20 -07:00
Andrew Kelley
a8065a05a5 stage2: fix implementation of liveness operandDies() 2020-07-20 13:12:20 -07:00
Andrew Kelley
896472c20e stage2: implement register copying 2020-07-20 13:12:20 -07:00
Andrew Kelley
ef9aeb6ac4 stage2: codegen: refactor to always have comptime arch 2020-07-20 13:12:20 -07:00
pfg
86922b8d08 stage2: support @"identifier" syntax 2020-07-16 14:08:36 -07:00
Vexu
37647375dc
translate-c: support initializer list expr macros 2020-07-16 16:20:47 +03:00
pfg
83a0073b68 stage2: period and suffixop 2020-07-16 04:22:05 -07:00
pfg
01ab167ce3 stage2: change large switch → inline for loop 2020-07-16 10:32:24 +00:00
Andrew Kelley
d29dd5834b stage2: local consts
These are now supported enough that this example code hits the
limitations of the register allocator:

fn add(a: u32, b: u32) void {
    const c = a + b; // 7
    const d = a + c; // 10
    const e = d + b; // 14
    assert(e == 14);
}
// error: TODO implement copyToNewRegister

So now the next step is to implement register allocation as planned.
2020-07-15 22:36:35 -07:00