2283 Commits

Author SHA1 Message Date
Alex Rønne Petersen
af1d777b27
std.builtin: add CallingConvention.sh_interrupt
Only supported in CBE.
2025-10-23 09:27:17 +02:00
Alex Rønne Petersen
4fa453ce20
std.builtin: add CallingConvention.microblaze_interrupt
Only supported in CBE.
2025-10-23 09:27:17 +02:00
Alex Rønne Petersen
abf40caeb7
std.builtin: add CallingConvention.msp430_interrupt
Supported by LLVM and CBE.
2025-10-23 09:27:17 +02:00
Alex Rønne Petersen
beb507a1ed
std.builtin: add CallingConvention.x86_64_x32
This was forgotten during the refactoring of std.builtin.CallingConvention. It
mirrors mips64_n32 for MIPS.
2025-10-23 09:27:17 +02:00
Alex Rønne Petersen
ee72f06f47
std.Target: add tags and info for alpha, hppa, microblaze, sh 2025-10-23 09:27:17 +02:00
Alex Rønne Petersen
3e2daa509a
std.Target: add arceb and xtensaeb Cpu.Arch tags 2025-10-23 09:27:17 +02:00
Alex Rønne Petersen
dbf9c7b548 compiler: add support for arc_interrupt calling convention
Only for use with the C backend at the moment.
2025-10-19 22:27:19 +02:00
Bingwu Zhang
6de339d5d3 cbe: fix MIPS register names in inline assembly
Zig uses "rN" for MIPS register clobbers which are more
ergonomic and easier to write (.rN vs. .@"$N").
However, GCC and Clang uses "$N".

Bug: #25613
Signed-off-by: Bingwu Zhang <xtex@xtexx.eu.org>
2025-10-19 01:07:51 +02:00
bnuuydev
173f497e29 llvm-backend: fix uefi data layout
the old logic caused the uefi case to fall through which caused an
assertion assertion in llvm to fail, as the data layout was wrong.
2025-10-16 13:59:02 +02:00
Jacob Young
2e31077fe0 Coff: implement threadlocal variables 2025-10-10 22:47:47 -07:00
Jacob Young
d28006153e llvm.Builder: allow Metadata to reference metadata strings
Closes #25486
2025-10-07 07:49:54 -04:00
Ryan Liptak
e393543e63 Support generating import libraries from mingw .def files without LLVM
For the supported COFF machine types of X64 (x86_64), I386 (x86), ARMNT (thumb), and ARM64 (aarch64), this new Zig implementation results in byte-for-byte identical .lib files when compared to the previous LLVM-backed implementation.
2025-10-03 18:26:05 -07:00
Jacob Young
07c3f9ef8e x86_64: fix bool vector init register clobber
Closes #25439
2025-10-03 12:18:53 -04:00
Jacob Young
1fa11e0954 Coff: delete 2025-10-02 17:44:52 -04:00
Jacob Young
e1f3fc6ce2 Coff2: create a new linker from scratch 2025-10-02 17:44:52 -04:00
Jacob Young
d5f09f56e0 x86_64: fix windows calling convention abi 2025-10-02 15:59:51 -04:00
Jacob Young
a896a22932 x86_64: fix @mulAdd miscomp 2025-09-27 20:10:32 -04:00
Jacob Young
a744fbd22f x86_64: fix ~/! miscomps 2025-09-27 18:30:52 -04:00
Jacob Young
b206b0626a x86_64: fix @floatFromInt miscomps 2025-09-27 18:30:52 -04:00
mlugg
611c38e6da x86_64: fix unencodable rem lowerings
The memory operand might use one of the extended GPRs R8 through R15 and
hence require a REX prefix, but having a REX prefix makes the high-byte
register AH unencodeable as the src operand. This latent bug was exposed
by this branch, presumably because `select` now happens to be putting
something in an extended GPR instead of a legacy GPR.

In theory this could be fixed with minimal cost by introducing a way to
communicate to `select` that neither the destination memory nor the
other temporary can be in an extended GPR. However, I just went for the
simple solution which comes at a cost of one trivial instruction: copy
the remainder from AH to AL, and *then* copy AL to the destination.
2025-09-27 18:30:52 -04:00
mlugg
77fca1652f x86_64: fix miscompilation of mul on vectors of large ints 2025-09-27 18:30:52 -04:00
mlugg
0c476191a4 x86_64: generate better constant memcpy code
`rep movsb` isn't usually a great idea here. This commit makes the logic
which tentatively existed in `genInlineMemcpy` apply in more cases, and
in particular applies it to the "new" backend logic. Put simply, all
copies of 128 bytes or fewer will now attempt this path first,
where---provided there is an SSE register and/or a general-purpose
register available---we will lower the operation using a sequence of 32,
16, 8, 4, 2, and 1 byte copy operations.

The feedback I got on this diff was "Push it to master and if it
miscomps I'll revert it" so don't blame me when it explodes
2025-09-27 18:30:52 -04:00
Alex Rønne Petersen
86077fe6bd compiler: move self-hosted backends from src/arch to src/codegen 2025-09-26 02:02:07 +02:00
Jacob Young
f58200e3f2 Elf2: create a new linker from scratch
This iteration already has significantly better incremental support.

Closes #24110
2025-09-21 14:09:14 -07:00
Frank Denis
bdc31c9561 aarch64/zonCast: don't return a pointer to a stack element
Elements are computed at comptime, so don't declare them as "var".
2025-09-21 05:01:41 -07:00
Jacob Young
5144f10ec9 aarch64: fix behavior failures 2025-09-20 18:33:01 -07:00
Jacob Young
f12c4f86fc aarch64: implement ptr_slice_*_ptr 2025-09-20 18:33:00 -07:00
Andrew Kelley
14bda4130a llvm backend: remove canElideLoad mechanism 2025-09-20 18:33:00 -07:00
mlugg
580b6d1fad llvm: fix tagged union payload size in debug info
Resolves: #24415
2025-09-16 18:55:19 +01:00
Andrew Kelley
150169f1e0 std.fmt: delete deprecated APIs
std.fmt.Formatter -> std.fmt.Alt
std.fmt.format -> std.Io.Writer.print
2025-08-31 12:49:18 -07:00
Andrew Kelley
b7104231af
Merge pull request #25077 from ziglang/GenericReader
std.Io: delete GenericReader, AnyReader, FixedBufferStream; and related API breakage
2025-08-30 12:43:52 -07:00
Alex Rønne Petersen
e351ee3b7f
Revert "llvm: workaround crashes in llvm loop optimizations"
This reverts commit b4fd57a9c114748afb9ba0a04bede61089a02ddf.

https://github.com/llvm/llvm-project/pull/149743
2025-08-30 06:36:41 +02:00
Alex Rønne Petersen
e4f38a611f
llvm: switch to native f16 IR type for all hexagon targets
This was fixed in LLVM 21, in particular for targets older than v68.
2025-08-30 06:36:41 +02:00
Alex Rønne Petersen
1c858ba7e3
llvm: remove f16 special case for soft float aarch64 2025-08-30 06:36:41 +02:00
Alex Rønne Petersen
d4882d10f8
llvm: switch to native f128 IR type for nvptx
LLVM 21 added support for this.
2025-08-30 06:36:41 +02:00
Alex Rønne Petersen
53c53a2697
llvm: switch to native f16 IR type for s390x
LLVM 21 added support for this.
2025-08-30 06:36:41 +02:00
Alex Rønne Petersen
2b84eb85ee
llvm: update data layout strings for LLVM 21 2025-08-30 06:36:41 +02:00
Alex Rønne Petersen
fdd32a2257
std.Target: add managarm OS tag 2025-08-30 06:36:41 +02:00
Andrew Kelley
79f267f6b9 std.Io: delete GenericReader
and delete deprecated alias std.io
2025-08-29 17:14:26 -07:00
Andrew Kelley
640c11171b LLVM backend:fix align 1 sret parameter load returned
closes #25067
2025-08-29 03:37:18 -07:00
Maciej 'vesim' Kuliński
ff859088e4 std.Target: add vita os
Co-authored-by: Alex Rønne Petersen <alex@alexrp.com>
2025-08-26 07:50:06 +02:00
Alex Rønne Petersen
5d019abe4e start adding big endian RISC-V support
The big endian RISC-V effort is mostly driven by MIPS (the company) which is
pivoting to RISC-V, and presumably needs a big endian variant to fill the niche
that big endian MIPS (the ISA) did.

GCC already supports these targets, but LLVM support will only appear in 22;
this commit just adds the necessary target knowledge and checks on our end.
2025-08-25 16:15:17 +02:00
GasInfinity
cc71936eb9 feat(std.Target): add 3ds os 2025-08-22 04:14:53 +02:00
Ali Cheraghi
2f422372b5 spirv: do not decorate nav alignment
they seem to be always `null` even when accessed through extern key so we have no way to tell whether they have natural alignment or not to decorate. And the reason we don't always decorate them is because some environments might be too dumb and crash for this.
2025-08-18 11:24:57 -07:00
Jacob Young
56d62395d1 aarch64: more assembler instructions
Closes #24848
2025-08-15 06:12:45 -04:00
Matthew Lugg
b87b958687
Merge pull request #24816 from mlugg/small-fixes
two small fixes
2025-08-13 23:55:21 +01:00
Matthew Lugg
a495628862
Merge pull request #24674 from Justus2308/undef-shift-bitwise
Sema: Improve comptime arithmetic undef handling
2025-08-13 14:04:59 +01:00
mlugg
ba6abd71c2
llvm: unions which are equivalent to enums are not by-ref
The LLVM backend lowers unions where all fields are zero-bit as
equivalent to their backing enum, and expects them to have the same
by-ref-ness in at least one place in the backend, probably more.

Resolves: #23577
2025-08-13 11:36:16 +01:00
mlugg
38ba425b26
llvm: support small error limits
Resolves: #23533
2025-08-13 11:36:16 +01:00
Isaac Freund
b8124d9c0b std.io.Writer.Allocating: rename getWritten() to written()
This "get" is useless noise and was copied from FixedBufferWriter.
Since this API has not yet landed in a release, now is a good time
to make the breaking change to fix this.
2025-08-13 01:43:52 -07:00