554 Commits

Author SHA1 Message Date
Andrew Kelley
597082adf4 Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgen
Conflicts:
 * build.zig
 * src/Compilation.zig
 * src/codegen/spirv/spec.zig
 * src/link/SpirV.zig
 * test/stage2/darwin.zig
   - this one might be problematic; start.zig looks for `main` in the
     root source file, not `_main`. Not sure why there is an underscore
     there in master branch.
2021-05-15 21:44:38 -07:00
Andrew Kelley
173142cc36
Merge pull request #8611 from shachaf/precedence
parser: Use an operator precedence table
2021-05-13 17:40:03 -04:00
Jakub Konka
402264ab0e Add experimental Darling support for cross testing macOS
* for cross testing stage2 tests, we use `darling shell` command
  since the path to the tested binary is relative to cwd
* for the `zig test` command, we simply use `darling` since the
  path to the binary is absolute
2021-05-13 20:31:33 +02:00
Andrew Kelley
c9cc09a3bf Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgen
Conflicts:
 * lib/std/os/linux.zig
 * lib/std/os/windows/bits.zig
 * src/Module.zig
 * src/Sema.zig
 * test/stage2/test.zig

Mainly I wanted Jakub's new macOS code for respecting stack size, since
we now depend on it for debug builds able to pass one of the test cases
for recursive comptime function calls with `@setEvalBranchQuota`.

The conflicts were all trivial.
2021-05-12 16:41:20 -07:00
LemonBoy
893a428656 stage2: Drop LLVM's host CPU detection method as fallback
The CPU detection code is nearly at feature parity, we do support
detecting the native CPU on Sparc systems and macos, our ARM/AArch64
model list is quite comprehensive and so is our PPC one.

The only missing pieces are:
- ARM32 detection on Darwin hosts (I don't think anybody is planning on
  running the compiler on a old-ass iPhone)
- s390x detection on Linux hosts, this can be easily added at a later
  stage.
2021-05-12 14:03:59 -04:00
LemonBoy
e260cfae85 stage2: Add CPU feature detection for macos
This is mostly meant to detect the current and future AArch64 core types
as the x86 part is already taken care of with OS-independent machinery.
2021-05-12 09:43:49 +02:00
Michael Dusan
30ace64fc4 bsd: detect os version
- netbsd, dragonly: use sysctlbyname
- openbsd: use sysctl
- updated default semver ranges
2021-05-11 22:05:08 -04:00
jacob gw
24dfa61236 stage1: remove outdated error message regarding #447 2021-05-10 21:00:10 +02:00
Andrew Kelley
5619ce2406 Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgen
Conflicts:
 * doc/langref.html.in
 * lib/std/enums.zig
 * lib/std/fmt.zig
 * lib/std/hash/auto_hash.zig
 * lib/std/math.zig
 * lib/std/mem.zig
 * lib/std/meta.zig
 * test/behavior/alignof.zig
 * test/behavior/bitcast.zig
 * test/behavior/bugs/1421.zig
 * test/behavior/cast.zig
 * test/behavior/ptrcast.zig
 * test/behavior/type_info.zig
 * test/behavior/vector.zig

Master branch added `try` to a bunch of testing function calls, and some
lines also had changed how to refer to the native architecture and other
`@import("builtin")` stuff.
2021-05-08 14:45:21 -07:00
Andrew Kelley
b6bb0ee1ac Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgen
Conflicts:
 * lib/std/os/linux/tls.zig
 * test/behavior/align.zig
 * test/behavior/atomics.zig
 * test/behavior/vector.zig
2021-05-08 10:53:22 -07:00
Veikka Tuominen
fd77f2cfed std: update usage of std.testing 2021-05-08 15:15:30 +03:00
Andrew Kelley
530e67cb86
Merge pull request #8683 from LemonBoy/thumblinux
Initial bringup for Linux/Thumb2
2021-05-06 12:50:34 -04:00
Andrew Kelley
fc40d23723 Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgen
Conflicts:
 * build.zig
 * lib/std/array_list.zig
 * lib/std/c/ast.zig
 * lib/std/c/parse.zig
 * lib/std/os/bits/linux.zig
2021-05-05 10:48:22 -07:00
Andrew Kelley
368e13a9a1
Merge pull request #8671 from LemonBoy/arm-host-det
ARM/AArch64 CPU host detection
2021-05-05 03:17:32 -04:00
LemonBoy
e863204c47 zig fmt: Fix edge case in inline asm parsing
The presence of a trailing comma in the single and only input/output
declaration confused the parser and made zig fmt discard any element
placed after the comma.
2021-05-05 03:16:07 -04:00
LemonBoy
afbcb6209d std: Initial bringup for Linux on Thumb2
There are some small problems here and there, mostly due to the pointers
having the lsb set and disrupting the fn alignment tests and the
`@FrameSize` implementation.
2021-05-04 18:52:53 +02:00
LemonBoy
3eed613407 std: Add two more ARM CPUs to the known CPU list
Modeled after GCC's description.
2021-05-03 12:32:13 +02:00
LemonBoy
e2d2295382 std: Add many more vendors and cpus to the ARM detection list
Hand-picked from GCC and LLVM lists.
2021-05-03 12:32:13 +02:00
LemonBoy
b10d40b89b stage2: Implement CPU host detection for ARM/AArch64 targets 2021-05-03 12:32:13 +02:00
Andrew Kelley
df24ce52b1 Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgen
In particular I wanted to take advantage of the new hex float parsing
code.
2021-04-28 14:57:38 -07:00
LemonBoy
da9da76e3f stage1: Implement CPU host detection for PowerPC targets
Untested but should work well on both 32 and 64 bit systems.
2021-04-27 13:11:39 -04:00
LemonBoy
7e6cc4c505 stage2: Ensure the features set is populated 2021-04-26 18:28:17 +02:00
LemonBoy
896d93e1e6 stage2: Add framework for host CPU detection on Linux
Add a generic framework to parse /proc/cpuinfo and implement the model
detection for 64bit SPARC targets as proof of concept.
2021-04-26 18:11:28 +02:00
Shachaf Ben-Kiki
33da465079 Use a directEnumArray lookup table instead of a switch 2021-04-24 23:03:48 -07:00
Shachaf Ben-Kiki
01aa74a93f parser: Use an operator precedence table
Instead of having one function per precedence level, mirroring the BNF grammar,
this uses the "precedence climbing" algorithm with a table of operator
precedences (and a few special cases that don't fit into the table as it is).

This is a first pass -- it's probably possible to put more of the parser
into this form, e.g. to support prefix/suffix operators with precedence, if
necessary, or just to simplify the code more.

It may also be possible to speed this up by putting more useful information
into the tokens during tokenization, to avoid the extra branch on the token in
operInfo.
2021-04-24 22:40:41 -07:00
Andrew Kelley
e86cee258c Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgen
In particular I wanted the change that makes `suspend;` illegal in the
parser.
2021-04-24 10:44:41 -07:00
LemonBoy
eabf378a56 zig fmt: Automagically fix block-less suspend exprs 2021-04-24 15:37:55 +02:00
LemonBoy
0aede1a8fc stage1: Require a block after suspend
Closes #8603
2021-04-24 10:25:43 +02:00
Andrew Kelley
30c9808391 AstGen: implement anytype parameters 2021-04-20 17:38:06 -07:00
Andrew Kelley
e315120b79 AstGen: implement array initialization expressions 2021-04-19 23:23:24 -07:00
Isaac Freund
4081e0a475 zig fmt: bypass auto indentation for // zig fmt: on
Currently an indented `// zig fmt: on` will be indented an additional
time on every run of zig fmt.
2021-04-17 20:10:20 -04:00
Andrew Kelley
429cd2b5dd std: change @import("builtin") to std.builtin 2021-04-15 19:06:39 -07:00
Michael Dusan
93cf9560b1
Merge remote-tracking branch 'origin/master' into llvm12 2021-04-11 17:40:19 -04:00
Isaac Freund
5b9ea5dd1e zig fmt: fix line comment detection
Previously hasComment() would consider a string literal "//" to be a
line comment. Fix this by only searching the bytes between tokens.
2021-04-10 23:10:24 +02:00
Lewis Gaul
ecf555c693
zig fmt: render array init on one line if no trailing comma
Continue to insert a trailing comma if there is a comment or multiline
string literal present.
2021-04-10 16:39:26 +02:00
LemonBoy
5ebcd8ccaf zig fmt: Fix rendering of arrays with single row
rowSize used to return null if all the elements were placed on the same
line as the right brace, making the rendering logic skip the whole set
of elements.

Given the usage of rowSize let's just drop the null and always return
the number of elements.

Fixes #8423
2021-04-09 10:03:45 -07:00
Andrew Kelley
2adeace905 std: modernize zig parser perf test
use the file size formatting functions
2021-04-06 22:34:48 -07:00
Andrew Kelley
a0e89c9b46 Merge remote-tracking branch 'origin/master' into llvm12 2021-04-02 12:09:38 -07:00
Andrew Kelley
b27d052676 stage2: finish source location reworkings in the branch
* remove the LazySrcLoc.todo tag
 * finish updating Sema and AstGen, remove the last of the
   `@panic("TODO")`.
2021-03-31 21:36:32 -07:00
Andrew Kelley
b85ef2300f Merge remote-tracking branch 'origin/master' into llvm12 2021-03-28 21:42:56 -07:00
LemonBoy
75080e351a std: Detect AMD Zen3 CPU family
Easy peasy lemon squeezy.
2021-03-27 12:23:40 -07:00
Andrew Kelley
31023de6c4 stage2: implement inline while
Introduce "inline" variants of ZIR tags:
 * block => block_inline
 * repeat => repeat_inline
 * break => break_inline
 * condbr => condbr_inline

The inline variants perform control flow at compile-time, and they
utilize the return value of `Sema.analyzeBody`.

`analyzeBody` now returns an Index, not a Ref, which is the ZIR index of
a break instruction. This effectively communicates both the intended
break target block as well as the operand, allowing parent blocks to
find out whether they, in turn, should return the break instruction up the
call stack, or accept the operand as the block's result and continue
analyzing instructions in the block.

Additionally:
 * removed the deprecated ZIR tag `block_comptime`.
 * removed `break_void_node` so that all break instructions use the same Data.
 * zir.Code: remove the `root_start` and `root_len` fields. There is now
   implied to be a block at index 0 for the root body. This is so that
   `break_inline` has something to point at and we no longer need the
   special instruction `break_flat`.
 * implement source location byteOffset() for .node_offset_if_cond
   .node_offset_for_cond is probably redundant and can be deleted.

We don't have `comptime var` supported yet, so this commit adds a test
that at least makes sure the condition is required to be comptime known
for `inline while`.
2021-03-25 00:55:36 -07:00
Isaac Freund
8111453cc1
astgen: implement array types 2021-03-22 14:54:13 +01:00
Andrew Kelley
56677f2f2d astgen: support blocks
We are now passing this test:

```zig
export fn _start() noreturn {}
```

```
test.zig:1:30: error: expected noreturn, found void
```

I ran into an issue where we get an integer overflow trying to compute
node index offsets from the containing Decl. The problem is that the
parser adds the Decl node after adding the child nodes. For some things,
it is easy to reserve the node index and then set it later, however, for
this case, it is not a trivial code change, because depending on tokens
after parsing the decl determines whether we want to add a new node or
not.

Possible strategies here:

1. Rework the parser code to make sure that Decl nodes are before
   children nodes in the AST node array.

2. Use signed integers for Decl node offsets.

3. Just flip the order of subtraction and addition. Expect Decl Node
   index to be greater than children Node indexes.

I opted for (3) because it seems like the simplest thing to do. We'll
want to unify the logic for computing the offsets though because if the
logic gets repeated, it will probably get repeated wrong.
2021-03-19 23:15:18 -07:00
Andrew Kelley
f5aca4a6a1 Merge remote-tracking branch 'origin/master' into zir-memory-layout
I need the enum arrays that were just merged into master.
2021-03-18 15:52:12 -07:00
Andrew Kelley
66245ac834 stage2: Module and Sema are compiling again
Next up is reworking the seam between the LazySrcLoc emitted by Sema
and the byte offsets currently expected by codegen.

And then the big one: updating astgen.zig to use the new memory layout.
2021-03-17 22:54:56 -07:00
Lewis Gaul
6787f163eb
zig fmt: don't add trailing whitespace on switch case 2021-03-16 09:26:28 +01:00
LemonBoy
5ecf8bddae
zig fmt: Respect line breaks in struct default value decls
Bring this in line with how variable declarations are handled.

Open a new indentation level for the initialization expression to handle
nested expressions like blocks.

Closes #7618
2021-03-16 09:22:16 +01:00
Andrew Kelley
aef3e534f5 stage2: *WIP*: rework ZIR memory layout; overhaul source locations
The memory layout for ZIR instructions is completely reworked. See
zir.zig for those changes. Some new types:

 * `zir.Code`: a "finished" set of ZIR instructions. Instead of allocating
   each instruction independently, there is now a Tag and 8 bytes of
   data available for all ZIR instructions. Small instructions fit
   within these 8 bytes; larger ones use 4 bytes for an index into
   `extra`. There is also `string_bytes` so that we can have 4 byte
   references to strings. `zir.Inst.Tag` describes how to interpret
   those 8 bytes of data.
   - This is shared by all `Block` scopes.

 * `Module.WipZirCode`: represents an in-progress `zir.Code`. In this
   structure, the arrays are mutable, and get resized as we add/delete
   things. There is extra state to keep track of things. This struct is
   stored on the stack. Once it is finished, it produces an immutable
   `zir.Code`, which will remain on the heap for the duration of a
   function's existence.
   - This is shared by all `GenZir` scopes.

 * `Sema`: represents in-progress semantic analysis of a `zir.Code`.
   This data is stored on the stack and is shared among all `Block`
   scopes. It is now the main "self" argument to everything in the file
   that was previously named `zir_sema.zig`.
   Additionally, I moved some logic that was in `Module` into here.

`Module.Fn` now stores its parameter names inside the `zir.Code`,
instead of inside ZIR instructions. When the TZIR memory layout
reworking time comes, codegen will be able to reference this data
directly instead of duplicating it.

astgen.zig is (so far) almost entirely untouched, but nearly all of it
will need to be reworked to adhere to this new memory layout structure.

I have no benchmarks to report yet, as I am still working through
compile errors and fixing various things that I broke in this branch.

Overhaul of Source Locations:

Previously we used `usize` everywhere to mean byte offset, but sometimes
also mean other stuff. This was error prone and also made us do
unnecessary work, and store unnecessary bytes in memory.

Now there are more types involved into source locations, and more ways
to describe a source location.

 * AllErrors.Message: embrace the assumption that files always have less
   than 2 << 32 bytes.
 * SrcLoc gets more complicated, to model more complicated source
   locations.
 * Introduce LazySrcLoc, which can model interesting source locations
   with very little stored state. Useful for avoiding doing unnecessary
   work when no compile errors occur.

Also, previously, we had `src: usize` on every ZIR instruction. This is
no longer the case. Each instruction now determines whether it even cares
about source location, and if so, how that source location is stored.
This requires more careful work inside `Sema`, but it results in fewer
bytes stored on the heap, without compromising accuracy and power of
compile error messages.

Miscellaneous:

 * std.zig: string literals have more helpful result values for
   reporting errors. There is now a lower level API and a higher level
   API.
   - side note: I noticed that the string literal logic needs some love.
     There is some unnecessarily hacky code there.
 * cut & pasted some TZIR logic that was in zir.zig to ir.zig. This
   probably broke stuff and needs to get fixed.
 * Removed type/Enum.zig, type/Union.zig, and type/Struct.zig. I don't
   think this quite how this code will be organized. Need some more
   careful planning about how to implement structs, unions, enums. They
   need to be independent Decls, just like a top level function.
2021-03-16 00:03:22 -07:00
Lewis Gaul
aa1c780560 Add test for multi-line while cont expr with same-line then expr 2021-03-15 20:44:45 +01:00