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Merge pull request #8671 from LemonBoy/arm-host-det
ARM/AArch64 CPU host detection
This commit is contained in:
Andrew Kelley
GitHub
commit
368e13a9a1
@ -75,8 +75,10 @@ pub fn spinLoopHint() callconv(.Inline) void {
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},
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.arm, .armeb, .thumb, .thumbeb => {
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// `yield` was introduced in v6k but are also available on v6m.
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const can_yield = comptime std.Target.arm.featureSetHas(std.Target.current.cpu.features, .has_v6m);
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if (can_yield) asm volatile ("yield" ::: "memory");
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const can_yield = comptime std.Target.arm.featureSetHasAny(std.Target.current.cpu.features, .{ .has_v6k, .has_v6m });
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if (can_yield) asm volatile ("yield" ::: "memory")
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// Fallback.
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else asm volatile ("" ::: "memory");
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},
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.aarch64, .aarch64_be, .aarch64_32 => {
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asm volatile ("isb" ::: "memory");
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@ -1621,6 +1621,16 @@ pub const cpu = struct {
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.apple_a7,
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}),
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};
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pub const emag = CpuModel{
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.name = "emag",
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.llvm_name = null,
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.features = featureSet(&[_]Feature{
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.crc,
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.crypto,
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.perfmon,
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.v8a,
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}),
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};
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pub const exynos_m1 = CpuModel{
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.name = "exynos_m1",
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.llvm_name = null,
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@ -1867,4 +1877,12 @@ pub const cpu = struct {
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.v8_2a,
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}),
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};
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pub const xgene1 = CpuModel{
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.name = "xgene1",
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.llvm_name = null,
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.features = featureSet(&[_]Feature{
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.perfmon,
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.v8a,
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}),
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};
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};
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@ -53,7 +53,7 @@ const SparcCpuinfoImpl = struct {
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// At the moment we only support 64bit SPARC systems.
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assert(self.is_64bit);
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const model = self.model orelse Target.Cpu.Model.generic(arch);
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const model = self.model orelse return null;
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return Target.Cpu{
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.arch = arch,
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.model = model,
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@ -65,7 +65,7 @@ const SparcCpuinfoImpl = struct {
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const SparcCpuinfoParser = CpuinfoParser(SparcCpuinfoImpl);
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test "cpuinfo: SPARC" {
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try testParser(SparcCpuinfoParser, &Target.sparc.cpu.niagara2,
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try testParser(SparcCpuinfoParser, .sparcv9, &Target.sparc.cpu.niagara2,
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\\cpu : UltraSparc T2 (Niagara2)
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\\fpu : UltraSparc T2 integrated FPU
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\\pmu : niagara2
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@ -119,7 +119,7 @@ const PowerpcCpuinfoImpl = struct {
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}
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fn finalize(self: *const PowerpcCpuinfoImpl, arch: Target.Cpu.Arch) ?Target.Cpu {
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const model = self.model orelse Target.Cpu.Model.generic(arch);
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const model = self.model orelse return null;
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return Target.Cpu{
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.arch = arch,
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.model = model,
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@ -131,13 +131,13 @@ const PowerpcCpuinfoImpl = struct {
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const PowerpcCpuinfoParser = CpuinfoParser(PowerpcCpuinfoImpl);
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test "cpuinfo: PowerPC" {
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try testParser(PowerpcCpuinfoParser, &Target.powerpc.cpu.@"970",
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try testParser(PowerpcCpuinfoParser, .powerpc, &Target.powerpc.cpu.@"970",
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\\processor : 0
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\\cpu : PPC970MP, altivec supported
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\\clock : 1250.000000MHz
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\\revision : 1.1 (pvr 0044 0101)
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);
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try testParser(PowerpcCpuinfoParser, &Target.powerpc.cpu.pwr8,
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try testParser(PowerpcCpuinfoParser, .powerpc64le, &Target.powerpc.cpu.pwr8,
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\\processor : 0
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\\cpu : POWER8 (raw), altivec supported
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\\clock : 2926.000000MHz
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@ -145,9 +145,275 @@ test "cpuinfo: PowerPC" {
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);
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}
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fn testParser(parser: anytype, expected_model: *const Target.Cpu.Model, input: []const u8) !void {
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const ArmCpuinfoImpl = struct {
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cores: [4]CoreInfo = undefined,
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core_no: usize = 0,
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have_fields: usize = 0,
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const CoreInfo = struct {
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architecture: u8 = 0,
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implementer: u8 = 0,
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variant: u8 = 0,
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part: u16 = 0,
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is_really_v6: bool = false,
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};
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const cpu_models = struct {
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// Shorthands to simplify the tables below.
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const A32 = Target.arm.cpu;
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const A64 = Target.aarch64.cpu;
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const E = struct {
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part: u16,
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variant: ?u8 = null, // null if matches any variant
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m32: ?*const Target.Cpu.Model = null,
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m64: ?*const Target.Cpu.Model = null,
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};
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// implementer = 0x41
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const ARM = [_]E{
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E{ .part = 0x926, .m32 = &A32.arm926ej_s, .m64 = null },
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E{ .part = 0xb02, .m32 = &A32.mpcore, .m64 = null },
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E{ .part = 0xb36, .m32 = &A32.arm1136j_s, .m64 = null },
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E{ .part = 0xb56, .m32 = &A32.arm1156t2_s, .m64 = null },
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E{ .part = 0xb76, .m32 = &A32.arm1176jz_s, .m64 = null },
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E{ .part = 0xc05, .m32 = &A32.cortex_a5, .m64 = null },
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E{ .part = 0xc07, .m32 = &A32.cortex_a7, .m64 = null },
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E{ .part = 0xc08, .m32 = &A32.cortex_a8, .m64 = null },
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E{ .part = 0xc09, .m32 = &A32.cortex_a9, .m64 = null },
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E{ .part = 0xc0d, .m32 = &A32.cortex_a17, .m64 = null },
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E{ .part = 0xc0f, .m32 = &A32.cortex_a15, .m64 = null },
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E{ .part = 0xc0e, .m32 = &A32.cortex_a17, .m64 = null },
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E{ .part = 0xc14, .m32 = &A32.cortex_r4, .m64 = null },
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E{ .part = 0xc15, .m32 = &A32.cortex_r5, .m64 = null },
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E{ .part = 0xc17, .m32 = &A32.cortex_r7, .m64 = null },
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E{ .part = 0xc18, .m32 = &A32.cortex_r8, .m64 = null },
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E{ .part = 0xc20, .m32 = &A32.cortex_m0, .m64 = null },
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E{ .part = 0xc21, .m32 = &A32.cortex_m1, .m64 = null },
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E{ .part = 0xc23, .m32 = &A32.cortex_m3, .m64 = null },
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E{ .part = 0xc24, .m32 = &A32.cortex_m4, .m64 = null },
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E{ .part = 0xc27, .m32 = &A32.cortex_m7, .m64 = null },
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E{ .part = 0xc60, .m32 = &A32.cortex_m0plus, .m64 = null },
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E{ .part = 0xd01, .m32 = &A32.cortex_a32, .m64 = null },
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E{ .part = 0xd03, .m32 = &A32.cortex_a53, .m64 = &A64.cortex_a53 },
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E{ .part = 0xd04, .m32 = &A32.cortex_a35, .m64 = &A64.cortex_a35 },
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E{ .part = 0xd05, .m32 = &A32.cortex_a55, .m64 = &A64.cortex_a55 },
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E{ .part = 0xd07, .m32 = &A32.cortex_a57, .m64 = &A64.cortex_a57 },
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E{ .part = 0xd08, .m32 = &A32.cortex_a72, .m64 = &A64.cortex_a72 },
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E{ .part = 0xd09, .m32 = &A32.cortex_a73, .m64 = &A64.cortex_a73 },
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E{ .part = 0xd0a, .m32 = &A32.cortex_a75, .m64 = &A64.cortex_a75 },
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E{ .part = 0xd0b, .m32 = &A32.cortex_a76, .m64 = &A64.cortex_a76 },
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E{ .part = 0xd0c, .m32 = &A32.neoverse_n1, .m64 = null },
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E{ .part = 0xd0d, .m32 = &A32.cortex_a77, .m64 = &A64.cortex_a77 },
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E{ .part = 0xd13, .m32 = &A32.cortex_r52, .m64 = null },
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E{ .part = 0xd20, .m32 = &A32.cortex_m23, .m64 = null },
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E{ .part = 0xd21, .m32 = &A32.cortex_m33, .m64 = null },
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E{ .part = 0xd41, .m32 = &A32.cortex_a78, .m64 = &A64.cortex_a78 },
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E{ .part = 0xd4b, .m32 = &A32.cortex_a78c, .m64 = &A64.cortex_a78c },
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E{ .part = 0xd44, .m32 = &A32.cortex_x1, .m64 = &A64.cortex_x1 },
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E{ .part = 0xd02, .m64 = &A64.cortex_a34 },
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E{ .part = 0xd06, .m64 = &A64.cortex_a65 },
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E{ .part = 0xd43, .m64 = &A64.cortex_a65ae },
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};
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// implementer = 0x42
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const Broadcom = [_]E{
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E{ .part = 0x516, .m64 = &A64.thunderx2t99 },
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};
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// implementer = 0x43
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const Cavium = [_]E{
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E{ .part = 0x0a0, .m64 = &A64.thunderx },
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E{ .part = 0x0a2, .m64 = &A64.thunderxt81 },
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E{ .part = 0x0a3, .m64 = &A64.thunderxt83 },
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E{ .part = 0x0a1, .m64 = &A64.thunderxt88 },
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E{ .part = 0x0af, .m64 = &A64.thunderx2t99 },
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};
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// implementer = 0x46
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const Fujitsu = [_]E{
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E{ .part = 0x001, .m64 = &A64.a64fx },
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};
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// implementer = 0x48
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const HiSilicon = [_]E{
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E{ .part = 0xd01, .m64 = &A64.tsv110 },
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};
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// implementer = 0x4e
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const Nvidia = [_]E{
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E{ .part = 0x004, .m64 = &A64.carmel },
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};
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// implementer = 0x50
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const Ampere = [_]E{
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E{ .part = 0x000, .variant = 3, .m64 = &A64.emag },
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E{ .part = 0x000, .m64 = &A64.xgene1 },
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};
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// implementer = 0x51
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const Qualcomm = [_]E{
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E{ .part = 0x06f, .m32 = &A32.krait },
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E{ .part = 0x201, .m64 = &A64.kryo, .m32 = &A64.kryo },
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E{ .part = 0x205, .m64 = &A64.kryo, .m32 = &A64.kryo },
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E{ .part = 0x211, .m64 = &A64.kryo, .m32 = &A64.kryo },
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E{ .part = 0x800, .m64 = &A64.cortex_a73, .m32 = &A64.cortex_a73 },
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E{ .part = 0x801, .m64 = &A64.cortex_a73, .m32 = &A64.cortex_a73 },
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E{ .part = 0x802, .m64 = &A64.cortex_a75, .m32 = &A64.cortex_a75 },
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E{ .part = 0x803, .m64 = &A64.cortex_a75, .m32 = &A64.cortex_a75 },
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E{ .part = 0x804, .m64 = &A64.cortex_a76, .m32 = &A64.cortex_a76 },
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E{ .part = 0x805, .m64 = &A64.cortex_a76, .m32 = &A64.cortex_a76 },
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E{ .part = 0xc00, .m64 = &A64.falkor },
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E{ .part = 0xc01, .m64 = &A64.saphira },
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};
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fn isKnown(core: CoreInfo, is_64bit: bool) ?*const Target.Cpu.Model {
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const models = switch (core.implementer) {
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0x41 => &ARM,
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0x42 => &Broadcom,
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0x43 => &Cavium,
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0x46 => &Fujitsu,
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0x48 => &HiSilicon,
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0x50 => &Ampere,
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0x51 => &Qualcomm,
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else => return null,
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};
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for (models) |model| {
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if (model.part == core.part and
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(model.variant == null or model.variant.? == core.variant))
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return if (is_64bit) model.m64 else model.m32;
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}
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return null;
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}
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};
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fn addOne(self: *ArmCpuinfoImpl) void {
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if (self.have_fields == 4 and self.core_no < self.cores.len) {
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if (self.core_no > 0) {
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// Deduplicate the core info.
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for (self.cores[0..self.core_no]) |it| {
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if (std.meta.eql(it, self.cores[self.core_no]))
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return;
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}
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}
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self.core_no += 1;
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}
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}
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fn line_hook(self: *ArmCpuinfoImpl, key: []const u8, value: []const u8) !bool {
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const info = &self.cores[self.core_no];
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if (mem.eql(u8, key, "processor")) {
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// Handle both old-style and new-style cpuinfo formats.
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// The former prints a sequence of "processor: N" lines for each
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// core and then the info for the core that's executing this code(!)
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// while the latter prints the infos for each core right after the
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// "processor" key.
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self.have_fields = 0;
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self.cores[self.core_no] = .{};
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} else if (mem.eql(u8, key, "CPU implementer")) {
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info.implementer = try fmt.parseInt(u8, value, 0);
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self.have_fields += 1;
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} else if (mem.eql(u8, key, "CPU architecture")) {
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// "AArch64" on older kernels.
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info.architecture = if (mem.startsWith(u8, value, "AArch64"))
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8
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else
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try fmt.parseInt(u8, value, 0);
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self.have_fields += 1;
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} else if (mem.eql(u8, key, "CPU variant")) {
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info.variant = try fmt.parseInt(u8, value, 0);
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self.have_fields += 1;
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} else if (mem.eql(u8, key, "CPU part")) {
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info.part = try fmt.parseInt(u16, value, 0);
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self.have_fields += 1;
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} else if (mem.eql(u8, key, "model name")) {
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// ARMv6 cores report "CPU architecture" equal to 7.
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if (mem.indexOf(u8, value, "(v6l)")) |_| {
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info.is_really_v6 = true;
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}
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} else if (mem.eql(u8, key, "CPU revision")) {
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// This field is always the last one for each CPU section.
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_ = self.addOne();
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}
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return true;
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}
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fn finalize(self: *ArmCpuinfoImpl, arch: Target.Cpu.Arch) ?Target.Cpu {
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if (self.core_no == 0) return null;
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const is_64bit = switch (arch) {
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.aarch64, .aarch64_be, .aarch64_32 => true,
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else => false,
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};
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var known_models: [self.cores.len]?*const Target.Cpu.Model = undefined;
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for (self.cores[0..self.core_no]) |core, i| {
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known_models[i] = cpu_models.isKnown(core, is_64bit);
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}
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// XXX We pick the first core on big.LITTLE systems, hopefully the
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// LITTLE one.
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const model = known_models[0] orelse return null;
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return Target.Cpu{
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.arch = arch,
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.model = model,
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.features = model.features,
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};
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}
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};
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const ArmCpuinfoParser = CpuinfoParser(ArmCpuinfoImpl);
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test "cpuinfo: ARM" {
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try testParser(ArmCpuinfoParser, .arm, &Target.arm.cpu.arm1176jz_s,
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\\processor : 0
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\\model name : ARMv6-compatible processor rev 7 (v6l)
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\\BogoMIPS : 997.08
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\\Features : half thumb fastmult vfp edsp java tls
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\\CPU implementer : 0x41
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\\CPU architecture: 7
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\\CPU variant : 0x0
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\\CPU part : 0xb76
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\\CPU revision : 7
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);
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try testParser(ArmCpuinfoParser, .arm, &Target.arm.cpu.cortex_a7,
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\\processor : 0
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\\model name : ARMv7 Processor rev 3 (v7l)
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\\BogoMIPS : 18.00
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\\Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae
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\\CPU implementer : 0x41
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\\CPU architecture: 7
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\\CPU variant : 0x0
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\\CPU part : 0xc07
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\\CPU revision : 3
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\\
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\\processor : 4
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\\model name : ARMv7 Processor rev 3 (v7l)
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\\BogoMIPS : 90.00
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\\Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae
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\\CPU implementer : 0x41
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\\CPU architecture: 7
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\\CPU variant : 0x2
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\\CPU part : 0xc0f
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\\CPU revision : 3
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);
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try testParser(ArmCpuinfoParser, .aarch64, &Target.aarch64.cpu.cortex_a72,
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\\processor : 0
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\\BogoMIPS : 108.00
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\\Features : fp asimd evtstrm crc32 cpuid
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\\CPU implementer : 0x41
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\\CPU architecture: 8
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\\CPU variant : 0x0
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\\CPU part : 0xd08
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\\CPU revision : 3
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);
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}
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fn testParser(
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parser: anytype,
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arch: Target.Cpu.Arch,
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expected_model: *const Target.Cpu.Model,
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input: []const u8,
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) !void {
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var fbs = io.fixedBufferStream(input);
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const result = try parser.parse(.powerpc, fbs.reader());
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const result = try parser.parse(arch, fbs.reader());
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testing.expectEqual(expected_model, result.?.model);
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testing.expect(expected_model.features.eql(result.?.features));
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}
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@ -186,6 +452,9 @@ pub fn detectNativeCpuAndFeatures() ?Target.Cpu {
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const current_arch = std.Target.current.cpu.arch;
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switch (current_arch) {
|
||||
.arm, .armeb, .thumb, .thumbeb, .aarch64, .aarch64_be, .aarch64_32 => {
|
||||
return ArmCpuinfoParser.parse(current_arch, f.reader()) catch null;
|
||||
},
|
||||
.sparcv9 => {
|
||||
return SparcCpuinfoParser.parse(current_arch, f.reader()) catch null;
|
||||
},
|
||||
|
||||
@ -239,6 +239,28 @@ const llvm_targets = [_]LlvmTarget{
|
||||
"zcz_fp",
|
||||
},
|
||||
},
|
||||
.{
|
||||
.llvm_name = null,
|
||||
.zig_name = "xgene1",
|
||||
.features = &.{
|
||||
"fp_armv8",
|
||||
"neon",
|
||||
"perfmon",
|
||||
"v8a",
|
||||
},
|
||||
},
|
||||
.{
|
||||
.llvm_name = null,
|
||||
.zig_name = "emag",
|
||||
.features = &.{
|
||||
"crc",
|
||||
"crypto",
|
||||
"fp_armv8",
|
||||
"neon",
|
||||
"perfmon",
|
||||
"v8a",
|
||||
},
|
||||
},
|
||||
},
|
||||
},
|
||||
.{
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user