12967 Commits

Author SHA1 Message Date
Isaac Freund
72bcdb639f
astgen: implement bool_and/bool_or 2021-03-22 00:51:25 +01:00
Isaac Freund
4cfd5f6a30 astgen: implement simple binary operators 2021-03-21 20:32:39 +01:00
Isaac Freund
310a44d5be zir: add negate/negate_wrap, implement astgen
These were previously implemented as a sub/sub_wrap instruction with a
lhs of 0. Making this separate instructions however allows us to save
some memory as there is no need to store a lhs.
2021-03-21 20:32:39 +01:00
Andrew Kelley
7800ae05a2 astgen: fix not detecting volatile asm
if only we could have compile errors for unused locals
2021-03-20 22:48:36 -07:00
Andrew Kelley
7598a00f34 stage2: fix memory management of ZIR code
* free Module.Fn ZIR code when destroying the owner Decl
 * unreachable_safe and unreachable_unsafe are collapsed into one ZIR
   instruction with a safety flag.
 * astgen: emit an unreachable instruction for unreachable literals
 * don't forget to call deinit on ZIR code
 * astgen: implement some builtin functions
2021-03-20 22:40:08 -07:00
Andrew Kelley
d8692b8bdb astgen: implement string literals 2021-03-20 21:59:28 -07:00
Andrew Kelley
8bad5dfa72 astgen: implement inline assembly 2021-03-20 21:48:35 -07:00
Andrew Kelley
260c610708 ZIR: move some un_tok tags to un_node instead
Idea here is to prefer un_node to un_tok in order to avoid unnecessary
calls to `tree.firstToken`.
2021-03-20 17:18:44 -07:00
Andrew Kelley
50010447bd astgen: implement function calls 2021-03-20 17:09:06 -07:00
jacob gw
907142a036 zir-memory-layout: remove all absolute src consts
this is to prevent future bugs
2021-03-20 15:56:59 -07:00
jacob gw
12eeb18a26 zir-memory-layout: astgen: more instructions 2021-03-20 15:56:59 -07:00
Timon Kruiper
a710368054 stage2: restructure LLVM backend
The LLVM backend is now structured into 3 different structs, namely
Object, DeclGen and FuncGen. Object represents an object that is
generated by the LLVM backend. DeclGen is responsible for generating
a decl and FuncGen is responsible for generating llvm instructions
from tzir in a function.
2021-03-20 15:10:44 -07:00
Andrew Kelley
56677f2f2d astgen: support blocks
We are now passing this test:

```zig
export fn _start() noreturn {}
```

```
test.zig:1:30: error: expected noreturn, found void
```

I ran into an issue where we get an integer overflow trying to compute
node index offsets from the containing Decl. The problem is that the
parser adds the Decl node after adding the child nodes. For some things,
it is easy to reserve the node index and then set it later, however, for
this case, it is not a trivial code change, because depending on tokens
after parsing the decl determines whether we want to add a new node or
not.

Possible strategies here:

1. Rework the parser code to make sure that Decl nodes are before
   children nodes in the AST node array.

2. Use signed integers for Decl node offsets.

3. Just flip the order of subtraction and addition. Expect Decl Node
   index to be greater than children Node indexes.

I opted for (3) because it seems like the simplest thing to do. We'll
want to unify the logic for computing the offsets though because if the
logic gets repeated, it will probably get repeated wrong.
2021-03-19 23:15:18 -07:00
Andrew Kelley
937c43ddf1 stage2: first pass at repairing ZIR printing 2021-03-19 19:33:11 -07:00
Andrew Kelley
0357cd8653 Sema: allocate inst_map with arena where appropriate 2021-03-19 15:31:50 -07:00
Andrew Kelley
81a935aef8 stage2: fix some math oopsies and typos 2021-03-19 15:19:47 -07:00
Andrew Kelley
132df14ee1 stage2: fix export source locations not being relative to Decl 2021-03-19 14:59:46 -07:00
jacob gw
a4f0ccdfe4 zir-memory-layout: astgen: literals and *, &
this was pretty low hanging fruit
2021-03-19 14:50:15 -07:00
jacob gw
c50397c268 llvm backend: use new srcloc
this allows to compile with ninja
2021-03-19 14:46:37 -07:00
jacob gw
e9810d9e79 zir-memory-layout: astgen: fill in identifier 2021-03-19 14:43:08 -07:00
Andrew Kelley
abdbc11c7e stage2: codegen: update asm IR to new names 2021-03-18 22:54:59 -07:00
Andrew Kelley
bd2154da3d stage2: the code is compiling again
(with a lot of things commented out)
2021-03-18 22:48:28 -07:00
Andrew Kelley
b2682237db stage2: get Module and Sema compiling again
There are some `@panic("TODO")` in there but I'm trying to get the
branch to the point where collaborators can jump in.

Next is to repair the seam between LazySrcLoc and codegen's expected
absolute file offsets.
2021-03-18 22:19:28 -07:00
Andrew Kelley
f5aca4a6a1 Merge remote-tracking branch 'origin/master' into zir-memory-layout
I need the enum arrays that were just merged into master.
2021-03-18 15:52:12 -07:00
Martin Wickham
96ae451bbe Add some enum utilities 2021-03-18 14:05:01 -07:00
Andrew Kelley
5e5b35f107 stage1: small memory optimization for simple pointer types
Avoid storing extra IR instruction data for simple pointer types.
2021-03-18 14:04:02 -07:00
Andrew Kelley
a6f5aa71ac stage1: small IR memory optimization on CheckSwitchProngs 2021-03-18 14:04:02 -07:00
Veikka Tuominen
ac7217e1f5 translate-c: preserve zero fractional part in float literals 2021-03-18 22:46:00 +02:00
jacob gw
7c6eb41619 cbe tests: fix test on windows
"\n" -> std.cstr.line_sep
2021-03-18 22:45:01 +02:00
Andrew Kelley
5cbb642525 stage1: small mem usage improvement for IR
move a boolean field to be represented implicitly with the enum tag.
Just borrowing one of the many strategies of stage2.

This simple change took the peak mem usage from std lib tests on
my machine from 8.21 GiB to 8.11 GiB.
2021-03-18 13:14:26 -07:00
Jakub Konka
17c066e925
Merge pull request #8282 from kubkon/zld
macho: upstream zld linker
2021-03-18 19:14:17 +01:00
Evan Haas
b54514d9dd
translate-c: Use [N:0] arrays when initializer is a string literal (#8264)
* translate-c: Use [N:0] arrays when initializer is a string literal

Translate incomplete arrays as [N:0] when initialized by a string literal.
This preserves a bit more of the type information from the original C program.

Fixes #8215
2021-03-18 14:41:04 +02:00
root
75a7abb0c4 std: Fix std.fs.path.joinZ 2021-03-18 14:33:38 +02:00
Veikka Tuominen
bcc97bc1ed
Merge pull request #8247 from Ersikan/fmt-fix-encoding
zig fmt: fix non-UTF-8 encoding #2820
2021-03-18 14:30:11 +02:00
Jakub Konka
f3b4f79c7f zld: temporarily disable testing shared lib linking 2021-03-18 11:10:31 +01:00
Jakub Konka
2cf1c1b96b macho: honor verbose_link when linking with zld 2021-03-18 11:10:09 +01:00
Jakub Konka
861ea64009 macho: remove now obsolete LLD fixups 2021-03-18 11:09:47 +01:00
Dimenus
dfeca48e35 @intCast takes two args 2021-03-17 22:58:52 -07:00
Andrew Kelley
66245ac834 stage2: Module and Sema are compiling again
Next up is reworking the seam between the LazySrcLoc emitted by Sema
and the byte offsets currently expected by codegen.

And then the big one: updating astgen.zig to use the new memory layout.
2021-03-17 22:54:56 -07:00
Jakub Konka
7516dfff83 zld: use zld when linking aarch64 by default and cross-comp 2021-03-18 00:37:13 +01:00
Jakub Konka
900658a85d rebase with master 2021-03-17 20:05:29 +01:00
Jakub Konka
1ec620be62 zld: fix GOT loads and indirection on x86_64 2021-03-17 19:59:57 +01:00
Jakub Konka
ac0c669473 zld: add/fix more issues
* fix debug info for static archives
* allow handling of empty object files
* fix some relocs for GOT loads
2021-03-17 19:59:13 +01:00
Jakub Konka
de209afbba zld: fix TLV initializers 2021-03-17 19:59:13 +01:00
Jakub Konka
349f878ecf zld: mimick Apple and add __DATA_CONST seg 2021-03-17 19:59:13 +01:00
Jakub Konka
62f43fbc06 zld: clean up use of commands.zig module 2021-03-17 19:59:13 +01:00
Jakub Konka
d484b3b3cb zld: use aarch64 for opcodes 2021-03-17 19:59:13 +01:00
Jakub Konka
dc34ac2b9e zld: fix incorrect offset calc for DICE 2021-03-17 19:59:13 +01:00
Jakub Konka
5d8944edc1 Revert log.warn hack 2021-03-17 19:59:13 +01:00
Jakub Konka
a1b0ec5277 zld: start bringing x64 up to speed 2021-03-17 19:59:13 +01:00