273 Commits

Author SHA1 Message Date
Jakub Konka
6461b95163 macho: fix DWARF in dSYM and sym naming more consistent
* Advance line and PC prior to ending sequence in debug line program
  for a fn_decl. This is equivalent to closing scope in the debugger
  and without it, the debugger will not map source-to-address info
  as a result will not print the source when breaking at a symbol.
* Fix debug aranges sentinels to be of the size as the actual tuple
  descriptor (assuming segment selector to be ommitted). In summary,
  the sentinels were 32bit 0s, whereas they ought to be 64bit 0s.
* Make naming of symbols in the binary more consistent by prefixing
  each symbol name with an underscore '_'.
2021-05-16 08:12:29 +02:00
Jakub Konka
00ebbe6df2 macho: require _main as global export in self-hosted
Clean up type and description flags generation for exports
in self-hosted MachO backend.
2021-05-14 13:08:56 +02:00
Jakub Konka
8eea5eddf7 macho: fix bug with symbol growth and realloc 2021-05-14 11:02:43 +02:00
Jakub Konka
53acb54fad
Bump zig-bootstrap and wasmtime versions in linux CI (#8738)
* Bump zig-bootstrap and wasmtime versions in linux CI

* Revert wasm stage2 test fixup; point to issue
2021-05-12 09:56:55 +02:00
joachimschmidt557
f2a3368891 stage2 ARM: Add spill registers test 2021-05-09 08:48:58 +02:00
Andrew Kelley
b88d381dec
Merge pull request #8474 from gracefuu/grace/encode-instruction
stage2 x86_64: encoding helpers, fix bugs
2021-05-09 01:36:51 -04:00
joachimschmidt557
bc06e19828 stage2 riscv64: cleanup code and add tests 2021-04-28 07:20:45 +02:00
gracefu
c4b83ea021
stage2 x86_64: implement integer mul
This was also an experiment to see if it were easier to implement a new
feature when using the instruction encoder.

Verdict: It's not that much easier, but I think it's certainly much more
readable, because the description of the Instruction annotates what each
field means. Right now, precise knowledge of x86_64 instructions is
still required because things like when to set the 64-bit flag, how to
read x86_64 instruction references, etc. are still not automatically
done for you.

In the future, this interface might make it sligtly easier to write an
assembler for x86_64, by abstracting the bit-fiddling aspects of
instruction encoding.
2021-04-16 15:21:17 +08:00
gracefu
5bd464e386
stage2 x86_64: use abi size to determine 64-bit operation
From my very cursory reading, it seems that the register manager doesn't
distinguish between registers that are physically the same but have
different sizes.

In that case, this means that during codegen, we can't rely on
`reg.size()` when determining the width of the operations we have to
perform. Instead, we must use some form of `ty.abiSize(self.target.*)`
to determine the size of the type we're operating with. If this size is
64 bits, then we should enable 64-bit operation.

This fixed a bug in the codegen for spilling instructions, which was
overwriting the previous stack entry with zeroes. See the modified test
case in this commit.
2021-04-16 15:21:17 +08:00
joachimschmidt557
4fe575f47b
stage2 ARM: Add fibonacci test 2021-04-11 10:19:36 +02:00
Andrew Kelley
f75cdd1acd
Merge pull request #8470 from ziglang/stage2-start
stage2: blaze the trail for std lib integration
2021-04-09 10:15:46 -07:00
jacob gw
afe5862111 stage2: add error for private decls accessed from other files 2021-04-09 10:05:15 -07:00
Andrew Kelley
91e1414b50 stage2: implement array access to a global array 2021-04-08 21:56:42 -07:00
Andrew Kelley
61b868f9a5 stage2: simplify Decl src_node field
Also fix "previous definition here" error notes to be correct.
2021-04-08 20:37:19 -07:00
Andrew Kelley
9f744f19e7
Merge pull request #8464 from gracefuu/grace/wasm-ops
stage2 wasm: Add division and bitwise/boolean ops &, |, ^, and, or
2021-04-08 13:41:49 -07:00
Andrew Kelley
d4f61f9842
Merge pull request #8449 from ziglang/stage2-enums
stage2: implement simple enums
2021-04-07 22:29:28 -07:00
Andrew Kelley
7595915775 stage2: add remaining enum compile error test cases 2021-04-07 22:24:52 -07:00
Andrew Kelley
57aa289fde Sema: fix switch validation '_' prong on wrong type 2021-04-07 22:19:17 -07:00
Andrew Kelley
e730172e47 stage2: fix switch validation of handling all enum values
There were several problems, all fixed:
 * AstGen was storing field names as references to the original
   source code bytes. However, that data would be destroyed when the
   source file is updated. Now, it correctly stores the field names in
   the Decl arena for the enum. The same fix applies to error set field
   names.
 * Sema was missing a memset inside `analyzeSwitch`, leaving the "seen
   enum fields" array with undefined memory. Now that they are all
   properly set to null, the validation works.
 * Moved the "enum declared here" note to the end. It looked weird
   interrupting the notes for which enum values were missing.
2021-04-07 22:02:45 -07:00
Andrew Kelley
b67378fb08 Sema: @intToEnum error msg includes a "declared here" hint 2021-04-07 21:04:55 -07:00
Andrew Kelley
a62e19ec8e AstGen: fix incorrect source loc for duplicate enum tag 2021-04-07 20:50:57 -07:00
Andrew Kelley
12087d4cba stage2: fix incremental compilation handling of parse errors
Before, incremental compilation would crash when trying to emit compile
errors for the update after introducing a parse error.

Parse errors are handled by not invalidating any existing semantic
analysis. However, only the parse error must be reported, with all the
other errors suppressed. Once the parse error is fixed, the new file can
be treated as an update to the previously-succeeded update.
2021-04-07 20:36:01 -07:00
Andrew Kelley
4996c2b6a9 stage2: fix incremental compilation Decl deletion logic
* `analyzeContainer` now has an `outdated_decls` set as well as
   `deleted_decls`. Instead of queuing up outdated Decls for re-analysis
   right away, they are added to this new set. When processing the
   `deleted_decls` set, we remove deleted Decls from the
   `outdated_decls` set, to avoid deleted Decl pointers from being in
   the work_queue. Only after processing the deleted decls do we add
   analyze_decl work items to the queue.

 * Module.deletion_set is now an `AutoArrayHashMap` rather than `ArrayList`.
   `declareDeclDependency` will now remove a Decl from it as appropriate.
   When processing the `deletion_set` in `Compilation.performAllTheWork`,
   it now assumes all Decl in the set are to be deleted.

 * Fix crash when handling parse errors. Currently we unload the
   `ast.Tree` if any parse errors occur. Previously the code emitted a
   LazySrcLoc pointing to a token index, but then when we try to resolve
   the token index to a byte offset to create a compile error message,
   the  ast.Tree` would be unloaded. Now we use
   `LazySrcLoc.byte_abs` instead of `token_abs` so the error message can
   be created even with the `ast.Tree` unloaded.

Together, these changes solve a crash that happened with incremental
compilation when Decls were added and removed in some combinations.
2021-04-07 19:54:28 -07:00
Andrew Kelley
8f28e26e7a Sema: implement switch validation for enums 2021-04-07 16:39:10 -07:00
gracefu
e4a60b63f2
stage2 wasm: Add bitwise/boolean ops &, |, ^, and, or 2021-04-08 05:27:00 +08:00
Andrew Kelley
18119aae30 Sema: implement comparison analysis for non-numeric types 2021-04-07 12:15:05 -07:00
Andrew Kelley
4e8fb9e6a5 Sema: DRY up enum field analysis and add "declared here" notes 2021-04-07 11:26:07 -07:00
Andrew Kelley
bcc371618f AstGen: fix @breakpoint ZIR
Previously it relied on the breakpoint ZIR instruction being void, but
that's no longer how things work.
2021-04-07 10:24:57 -07:00
jacob gw
01a39fa1d4 stage2: coerce enum_literal -> enum 2021-04-07 07:19:11 -04:00
gracefu
869fc06c57
stage2 wasm: codegen mul op 2021-04-05 14:37:04 +08:00
gracefu
d1244d3608
stage2 wasm: codegen sub op 2021-04-05 14:37:04 +08:00
Andrew Kelley
2f07d76eee stage2: implement Type.onePossibleValue for structs 2021-04-02 21:17:23 -07:00
Andrew Kelley
d47f0abd5b stage2: Sema: implement validate_struct_init_ptr 2021-04-02 21:06:09 -07:00
Andrew Kelley
97d7fddfb7 stage2: progress towards basic structs
Introduce `ResultLoc.none_or_ref` which is used by field access
expressions to avoid unnecessary loads when the field access itself
will do the load. This turns:

```zig
p.y - p.x - p.x
```

from

```zir
  %14 = load(%4) node_offset:8:12
  %15 = field_val(%14, "y") node_offset:8:13
  %16 = load(%4) node_offset:8:18
  %17 = field_val(%16, "x") node_offset:8:19
  %18 = sub(%15, %17) node_offset:8:16
  %19 = load(%4) node_offset:8:24
  %20 = field_val(%19, "x") node_offset:8:25
```

to

```zir
  %14 = field_val(%4, "y") node_offset:8:13
  %15 = field_val(%4, "x") node_offset:8:19
  %16 = sub(%14, %15) node_offset:8:16
  %17 = field_val(%4, "x") node_offset:8:25
```

Much more compact. This requires `Sema.zirFieldVal` to support both
pointers and non-pointers.

C backend: Implement typedefs for struct types, as well as the following
TZIR instructions:
 * mul
 * mulwrap
 * addwrap
 * subwrap
 * ref
 * struct_field_ptr

Note that add, addwrap, sub, subwrap, mul, mulwrap instructions are all
incorrect currently and need to be updated to properly handle wrapping
and non wrapping for signed and unsigned.

C backend: change indentation delta to 1, to make the output smaller and
to process fewer bytes.

I promise I will add a test case as soon as I fix those warnings that
are being printed for my test case.
2021-04-02 19:11:51 -07:00
Andrew Kelley
070a28e493
Merge pull request #8266 from ziglang/zir-memory-layout
rework ZIR memory layout; overhaul source locations
2021-03-31 23:11:15 -07:00
Andrew Kelley
c9e31febf8 stage2: finish implementation of LazySrcLoc 2021-03-31 23:00:00 -07:00
Andrew Kelley
e8143f6cbe stage2: compile error for duplicate switch value on sparse 2021-03-31 18:39:34 -07:00
Andrew Kelley
cec766f73c stage2: compile error for duplicate switch value on boolean 2021-03-31 18:30:23 -07:00
jacob gw
fedc9ebd26 stage2: cbe: restore all previously passing tests! 2021-03-31 18:09:45 -07:00
Andrew Kelley
3cebaaad1c astgen: improved handling of coercion
GenZir struct now has rl_ty_inst field which tracks the result location
type (if any) a block expects all of its results to be coerced to.

Remove a redundant coercion on const local initialization with a
specified type.

Switch expressions, during elision of store_to_block_ptr instructions,
now re-purpose them to be type coercion when the block has a type in the
result location.
2021-03-31 18:05:37 -07:00
Andrew Kelley
08eedc962d Sema: fix else case code generation for switch 2021-03-31 16:17:47 -07:00
joachimschmidt557
1b657e6e41 stage2 codegen: Make sure function return value is in a callee
preserved register
2021-03-31 23:27:50 +02:00
Andrew Kelley
281a7baaea Merge remote-tracking branch 'origin/master' into zir-memory-layout
Wanted to make sure those new test cases still pass.

Also grab that CI fix so we can get those green check marks.
2021-03-28 19:42:43 -07:00
Andrew Kelley
8f469c1127 stage2: fix error sets 2021-03-28 19:40:21 -07:00
jacob gw
0005b34637 stage2: implement sema for @errorToInt and @intToError 2021-03-28 18:22:01 -07:00
Andrew Kelley
68f4eb0f67 stage2: fully implement Type.eql for pointers
Also fixed abiAlignment - for pointers it was returning the abi
alignment inside the type, rather than of the pointer itself. There is
now `ptrAlignment` for getting the alignment inside the type of
pointers.
2021-03-27 23:55:19 -07:00
Andrew Kelley
95cc457d97 stage2: enable passing tests 2021-03-26 23:54:36 -07:00
Andrew Kelley
1f5617ac07 stage2: implement bitwise expr and error literals 2021-03-26 23:46:37 -07:00
Andrew Kelley
da731e18c9 stage2: implement source location: .node_offset_var_decl_ty 2021-03-26 18:35:15 -07:00
Andrew Kelley
a72bfd00cf astgen: fix continue expressions 2021-03-26 18:26:39 -07:00