6242 Commits

Author SHA1 Message Date
Luuk de Gram
424f260f85 Fix wasm-related compile errors:
- Update `fail()` to not require a `srcLoc`.
This brings it in line with other backends, and we were always passing 'node_offset = 0', anyway.
- Fix unused local due to change of architecture wrt function/decl generation.
- Replace all old instructions to indexes within the function signatures.
2021-07-20 12:19:16 -07:00
Andrew Kelley
8082660118 stage2: codegen.zig updated to new AIR memory layout 2021-07-20 12:19:16 -07:00
Andrew Kelley
eadbee2041 stage2: first pass at printing AIR/Liveness to text
* some instructions are not implemented yet
 * fix off-by-1 in Air.getMainBody
 * Compilation: use `@import("builtin")` rather than `std.builtin`
   for the values that are different for different build configurations.
 * Sema: avoid calling `addType` in between
   air_instructions.ensureUnusedCapacity and corresponding
   appendAssumeCapacity because it can possibly add an instruction.
 * Value: functions print their names
2021-07-20 12:19:16 -07:00
Andrew Kelley
12c10139e3 Sema: finish reworking for AIR memory layout except switch 2021-07-20 12:19:16 -07:00
Andrew Kelley
0da6633909 Sema: fix implementation of getTypeOf
and rename it to typeOf
2021-07-20 12:19:16 -07:00
Andrew Kelley
1294ebe1f5 Sema: AIR memory layout reworking for noreturn instructions 2021-07-20 12:19:16 -07:00
Andrew Kelley
c020a30296 Sema: remove br_block_flat AIR instruction
Thanks to the new AIR memory layout, we can do this by turning a br
operand into a block, rather than having this special purpose
instruction.
2021-07-20 12:19:16 -07:00
Andrew Kelley
27be4f3140 Sema: more AIR memory layout reworking progress
Additionally: ZIR encoding for floats now supports float literals up to
f64, not only f32. This is because we no longer need a source location
for this instruction.
2021-07-20 12:19:16 -07:00
Andrew Kelley
7bb2d13a09 stage2: remove ZIR instructions bool_and and bool_or
These were unused. I believe this happened with the introduction of
bool_br_and and bool_br_or instructions.
2021-07-20 12:19:16 -07:00
Andrew Kelley
3c5927fb87 Sema: add a strategy for handling costly source locations
Now you can pass `.unneeded` for a `LazySrcLoc` and if there ended up
being a compile error that needed it, you'll get
`error.NeededSourceLocation`.

Callsites can now exploit this error to do the expensive computation
to produce a source location object and then repeat the operation.
2021-07-20 12:19:16 -07:00
Andrew Kelley
dbd3529d1f Sema: first pass reworking for AIR memory layout 2021-07-20 12:19:16 -07:00
Andrew Kelley
f17a05bfb7 CLI: add plan9 -ofmt help text 2021-07-20 12:19:16 -07:00
Jacob G-W
91b1896184 plan9 linker: make more incremental
The incrementalness is now roughly the same as the c backend
rather than the spirv backend before.
2021-07-20 12:19:16 -07:00
Jacob G-W
3a41e4430e codegen: add FnResult type which is a Result that removes externally_managed 2021-07-20 12:19:16 -07:00
Andrew Kelley
c09b973ec2 stage2: compile error fixes for AIR memory layout branch
Now the branch is compiling again, provided that one uses
`-Dskip-non-native`, but many code paths are disabled. The code paths
can now be re-enabled one at a time and updated to conform to the new
AIR memory layout.
2021-07-20 12:19:16 -07:00
Andrew Kelley
0f38f68696 stage2: Air and Liveness are passed ephemerally
to the link infrastructure, instead of being stored with Module.Fn. This
moves towards a strategy to make more efficient use of memory by not
storing Air or Liveness data in the Fn struct, but computing it on
demand, immediately sending it to the backend, and then immediately
freeing it.

Backends which want to defer codegen until flush() such as SPIR-V
must move the Air/Liveness data upon `updateFunc` being called and keep
track of that data in the backend implementation itself.
2021-07-20 12:19:16 -07:00
Andrew Kelley
913393fd3b stage2: first pass over Module.zig for AIR memory layout 2021-07-20 12:19:16 -07:00
Andrew Kelley
ee6432537e stage2: first pass over codegen.zig for AIR memory layout 2021-07-20 12:19:16 -07:00
Andrew Kelley
ef7080aed1 stage2: update Liveness, SPIR-V for new AIR memory layout
also do the inline assembly instruction
2021-07-20 12:19:16 -07:00
Andrew Kelley
9918a5fbe3 AstGen: remove unneeded field ref_start_index
Previously, this field was used because the Zir.Inst.Ref encoding
supported the concept of references to function parameters. However now
thanks to whole-file-astgen, the implementations of indexToRef and
refToIndex are trivial addition/subtraction of a comptime const integer.
2021-07-20 12:19:14 -07:00
Andrew Kelley
3c3abaf390 stage2: update liveness analysis to new AIR memory layout
It's pretty compact, with each AIR instruction only taking up 4 bits,
plus a sparse table for special instructions such as conditional branch,
switch branch, and function calls with more than 2 arguments.
2021-07-20 12:18:14 -07:00
Andrew Kelley
5d6f7b44c1 stage2: rework AIR memory layout
This commit changes the AIR file and the documentation of the memory
layout. The actual work of modifying the surrounding code (in Sema and
codegen) is not yet done.
2021-07-20 12:18:14 -07:00
Loris Cro
e807020679 Fixed wrong "unable to load" error for non-existing import files
- Changed ZIR encoding of `import` metadata from having instruction
  indexes to storing token indexes.
2021-07-19 23:23:42 -04:00
Evan Haas
3e67ef5c9f translate-c: Handle underscore when used as an identifier
Use `@` syntax to escape `_` when used as an identifier.

Remove the stage1 astgen prohibition against assigning from `_`

Note: there a few stage1 bugs preventing `_` from being used as an identifier
for a local variable or function parameter; these will be fixed by stage2.
They are unlikely to arise in real C code since identifiers starting with
underscore are reserved for the implementation.
2021-07-19 12:56:23 +03:00
Jay Petacat
9979741bff stage1: Fix OsOther by adding missing OsPlan9 2021-07-16 19:35:25 -04:00
Daniele Cocca
b009aca38a src: return a null-terminated slice 2021-07-15 15:12:44 -04:00
leesongun
132b18e2b3
Fix bigint_shl (#9305) 2021-07-13 10:16:57 +03:00
Jacob G-W
74972531b5 fix doc comment in translate_c 2021-07-13 10:12:31 +03:00
Andrew Kelley
28dd9d478d C backend: TypedefMap is now ArrayHashMap
The C backend depends on insertion order into this map so that type
definitions will be declared before they are used.
2021-07-12 12:40:32 -07:00
Martin Wickham
bd1689ae89 Remove Stage1AirInst::owner_bb, use zir owner instead. 2021-07-11 19:16:57 -05:00
Andrew Kelley
7ef8546826
Merge pull request #9352 from g-w1/fix-9346
stage2 astgen: error for return outside of function scope
2021-07-11 15:11:28 -04:00
Jacob G-W
b0b9c3c2dc stage2: remove redundancy from error message
invalid 'try' outside function scope ->
'try' outside function scope
2021-07-11 10:03:47 -04:00
Jacob G-W
18770721ac stage2 astgen: error for return outside of function scope 2021-07-11 10:03:35 -04:00
Martin Wickham
75d1b113aa Rename IrInstSrc to Stage1ZirInst and IrInstGen to Stage1AirInst 2021-07-11 02:00:04 -04:00
Jacob G-W
968d1ecf17 stage2 plan9: add aarch64 support 2021-07-11 01:58:26 -04:00
Andrew Kelley
40764650af stage1: avoid wasting padding with IR instruction tag
For stage1 ZIR instructions and stage1 AIR instructions, the instruction
op code was taking up 8 bytes due to padding even though it only needed
1 byte. This commit reduces the ref_count field from uint32_t to
uint16_t because the code only really cares if instructions are
referenced at all, not how many times they are referenced. With the
ref_count field reduced to uint16_t the uint8_t op code is now placed in
the freed up space.

Empirically, this saves 382 MiB of peak RAM usage when building the
self-hosted compiler, which is a reduction of 5%. Consequently this
resulted in a 3% reduction of cache-misses when building the self-hosted
compiler.

This was @SpexGuy's idea, committed by me because we tested it on my
computer.
2021-07-10 15:38:13 -07:00
Takeshi Yoneda
b9e896d7b0 wasi-libc: remove crt1.o as it's not WASI ABI compatible
Signed-off-by: Takeshi Yoneda <takeshi@tetrate.io>
2021-07-11 00:06:47 +02:00
Martin Wickham
2d855745f9 Fix libc include directories for the MSVC target 2021-07-10 17:00:42 -04:00
Martin Wickham
84a544f96c Fix argument forwarding to LLVM on Windows 2021-07-10 15:58:38 -04:00
Andrew Kelley
476faef97a plan9 cleanups
* rename files to adhere to conventions
 * remove unnecessary function / optionality
 * fix merge conflict
 * better panic message
 * remove unnecessary TODO comment
 * proper namespacing of declarations
 * clean up documentation comments
 * no copyright header needed for a brand new zig file that is not
   copied from anywhere
2021-07-08 14:24:16 -07:00
Jacob G-W
4eb778fc3e plan9 linker: remove unused stuff 2021-07-08 14:12:08 -07:00
Jacob G-W
1c2facaf6b stage2: include enough inline asm support for more plan9 syscalls
Also make the exit more correct by exiting 0 rather than random
stuff on the stack.
2021-07-08 14:12:08 -07:00
Jacob G-W
f1aadfa77b plan9 linker: remove panics and improve 64 bit support
Don't @intCast when we do not need to, and change
some panics to unreachable when they can never happen.
2021-07-08 14:12:08 -07:00
Jacob G-W
db2d5b49c6 plan9 linker: use a global offset table
this simplifies stuff and makes us not have to use relocations
2021-07-08 14:12:07 -07:00
Jacob G-W
166dffb088 plan9 linker: correct runtime vs file offset converting code 2021-07-08 14:10:50 -07:00
Jacob G-W
72bb6bb143 plan9 linker: produce an object file that can actually work!!! 2021-07-08 14:10:49 -07:00
Jacob G-W
3e59c15025 plan9 linker: do relocations 2021-07-08 14:10:49 -07:00
Jacob G-W
c114474190 plan9 linker: write symbol table
Also switch to iovecs because gotta go fast.
2021-07-08 14:10:49 -07:00
Jacob G-W
798162e509 plan9 linker: make runnable binaries
We can now run binaries! (they segfault, but still run!)
2021-07-08 14:10:49 -07:00
jacob gw
34c21affa2 initial plan9 boilerplate
The code now compiles and fails with Plan9ObjectFormatUnimplemented
2021-07-08 14:10:49 -07:00