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3649 Commits

Author SHA1 Message Date
LemonBoy
958f00f1c7 Don't generate any type info for void return types 
Closely matches what the LLVM debug emitter expects, the generated DWARF
infos are now standard-compliant.
 2020-02-02 15:30:12 -05:00
Andrew Kelley
58c97b3561
fix llvm assertion with debug info for vectors 2020-01-30 15:30:38 -05:00
Andrew Kelley
f97b398b65
simplify int/float comparison 2020-01-29 17:20:41 -05:00
LemonBoy
fe4ef7b461
Fix comptime float-int comparisons 
Closes #4259
 2020-01-29 16:37:55 -05:00
Valentin Anger
d448c3d38a Add support for code model selection 2020-01-29 16:09:07 -05:00
LemonBoy
59bc1d2721 Fix edge case in switch with single else 
ir_gen_switch_expr doesn't set the switch_br field at all if there are
zero cases, detect this situation and handle it gracefully.

Closes #4322
 2020-01-29 16:05:14 -05:00
Andrew Kelley
4fad16284e
Merge pull request #4320 from fengb/while-spills 
Add async spills to while captured variables
 2020-01-29 13:37:58 -05:00
Benjamin Feng
a4ac7980b4 Add a spill to while error union 2020-01-29 10:01:51 -06:00
Benjamin Feng
2f239e3dbd Add a spill to while optional 2020-01-28 23:36:43 -06:00
LemonBoy
3ec37c979e Build compiler_rt/c with optimizations if possible 2020-01-28 19:28:39 -05:00
Andrew Kelley
504ce86ac9
fix more compile error test regressions 2020-01-28 14:17:25 -05:00
Andrew Kelley
793d81c4e8
fix result locations not handling undefined correctly 2020-01-28 13:33:51 -05:00
Andrew Kelley
86da9346e4
fix error message column/line number regressions 2020-01-28 13:25:49 -05:00
Andrew Kelley
e0000c47bd
fix regression of storing optional with 0-bit payload 2020-01-28 12:32:39 -05:00
Andrew Kelley
5c55a9b4e8
fix compile error regression with struct containing itself 2020-01-28 11:52:48 -05:00
Andrew Kelley
287d3c37e1
fix 0-bit child type coerced to optional return ptr result location 
by un-special-casing 0 bit types in result locations
 2020-01-28 11:39:36 -05:00
Andrew Kelley
8710fdbf39
fix line, column numbers of compile errors 2020-01-27 22:05:27 -05:00
Andrew Kelley
ae20574d5e
add missing spill for for loops with pointer elems 2020-01-27 21:30:11 -05:00
Andrew Kelley
c58633ef17
fix assertion with var debug loc not initialized 2020-01-27 20:56:24 -05:00
Andrew Kelley
9d59cdb8c1
fix auto created variables not having correct alignment 2020-01-27 19:42:32 -05:00
Andrew Kelley
37ab960492
fix not handling undefined u0 correctly 2020-01-27 18:59:46 -05:00
Andrew Kelley
b38b967844
fix triple level result location with bitcast sandwich 
...passed as tuple element
 2020-01-27 18:26:39 -05:00
Andrew Kelley
b96872ef2f
@bitCast result location: fix passing invalid alignment 
when the value has 0 bits
 2020-01-27 17:45:29 -05:00
Andrew Kelley
c0fee9dfc7
fix nested bitcast passed as tuple element 2020-01-27 17:30:39 -05:00
Andrew Kelley
e2778c03e0
Merge branch 'master' into ir-clean-up-vars 2020-01-27 13:32:39 -05:00
Andrew Kelley
f41e50dc08
Merge branch 'fx-4274' of https://github.com/LemonBoy/zig into LemonBoy-fix-4274 2020-01-27 09:52:31 -05:00
Andrew Kelley
d9fb6c2054
fix compilation error 2020-01-26 00:55:04 -05:00
Andrew Kelley
9dffc369f1
Merge remote-tracking branch 'origin/master' into layneson-cpus_and_features 2020-01-25 23:25:29 -05:00
Andrew Kelley
4e9b1f5479
Merge pull request #4290 from ziglang/split-ir-structs 
split IrInstruction into IrInst, IrInstSrc, IrInstGen
 2020-01-25 23:24:41 -05:00
Andrew Kelley
32f0039b43
fix memory profiling 2020-01-25 22:02:10 -05:00
Andrew Kelley
6aac423964
split IrInstruction into IrInst, IrInstSrc, IrInstGen 
This makes it so that less memory is used for IR instructions, as well
as catching bugs when one expected one kind of instruction and received
the other.
 2020-01-25 21:49:32 -05:00
Feix Weiglhofer
a4a9330648 translate-c: Don't make const parameters mutable. (#4273) 
* translate-c: Remove arg-prefix from const parameters.
* translate-c: Add unittest for const parameters.
 2020-01-24 15:32:32 -05:00
Michael Dusan
aa75df36df
Merge pull request #4279 from mikdusan/create-global-cache 
stage1: make sure to create native_libc.txt dir
 2020-01-24 00:31:18 -05:00
Tadeo Kondrak
3d8328abce Don't include stdbool.h for void and unreachable 
Fixes https://github.com/ziglang/zig/issues/4272
 2020-01-23 23:24:45 -05:00
Michael Dusan
b54040d394
stage1: make sure to create native_libc.txt dir 
- fix regression from #4186
 2020-01-23 21:59:28 -05:00
LemonBoy
8d9b8ab930 More error checking for unresolved TLDs 
Closes #4274
 2020-01-23 22:40:12 +01:00
Andrew Kelley
fbfda7f00e
fix incorrect list of sub-arches for aarch64 
tests use older sub-arch that works in the older qemu
 2020-01-23 13:02:45 -05:00
Andrew Kelley
9845264a0b
aarch64: less feature-full baseline CPU 2020-01-22 18:40:34 -05:00
LemonBoy
a284be3f69 Fix unsafe cast in translate_c 
Fixes #4250
 2020-01-22 17:58:57 -05:00
Andrew Kelley
3227aec848
fix not respecting sub-arch feature 2020-01-22 17:35:57 -05:00
Andrew Kelley
48c7e6c48b
std.Target.CpuFeatures is now a struct with both CPU and feature set 
Previously it was a tagged union which was one of:
 * baseline
 * a specific CPU
 * a set of features

Now, it's possible to have a CPU but also modify the CPU's feature set
on top of that. This is closer to what LLVM does.

This is more correct because Zig's notion of CPUs (and LLVM's) is not
exact CPU models. For example "skylake" is not one very specific model;
there are several different pieces of hardware that match "skylake" that
have different feature sets enabled.
 2020-01-22 17:13:31 -05:00
Andrew Kelley
830e0ba2d2 enable native CPU feature for windows; disable failing tests 
See #508. These can be re-enabled when we upgrade to LLVM 10.
 2020-01-21 21:46:06 -05:00
Andrew Kelley
6e6ec3d71d put hack back in to disable windows native cpu features 
See #508. This can be removed when we upgrade to LLVM 10.
 2020-01-21 21:01:36 -05:00
Andrew Kelley
92559cd02c
hit a comptime limitation with computing dense sets 2020-01-21 19:40:44 -05:00
Andrew Kelley
15d5cab569
fix target_triple_zig to emit zig-compatible triples 2020-01-21 12:25:22 -05:00
Andrew Kelley
327ad0ae89
target_triple_llvm: emit none instead of unknown 2020-01-21 03:05:56 -05:00
Andrew Kelley
1f7babbc80
properly forward baseline target cpu features to llvm 2020-01-21 03:01:20 -05:00
Andrew Kelley
39759b90fc
make zig targets show native cpu name and features 2020-01-21 01:22:37 -05:00
Andrew Kelley
e640d01535
fixups to arch data, support any number of cpu features 2020-01-21 00:34:54 -05:00
Andrew Kelley
f3dd9bbdac
improve zig targets 2020-01-20 13:40:25 -05:00