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llvm: Disable f16 lowering for hexagon.

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In theory, this should work for v68+. In practice, it runs into an LLVM
assertion when using a `freeze` instruction on `f16` values, similar to the
issue we had for LoongArch.
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Alex Rønne Petersen 2024-10-02 08:16:05 +02:00
parent 56b0c7bd2f
commit f31173d379
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src/codegen/llvm.zig
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@ -12380,6 +12380,7 @@ fn backendSupportsF80(target: std.Target) bool {
/// if it produces miscompilations.
fn backendSupportsF16(target: std.Target) bool {
return switch (target.cpu.arch) {
.hexagon,
.powerpc,
.powerpcle,
.powerpc64,