From f31173d379eb7c63f214579ffbba611c1fa38900 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= <alex@alexrp.com>
Date: Wed, 2 Oct 2024 08:16:05 +0200
Subject: [PATCH] llvm: Disable f16 lowering for hexagon.

In theory, this should work for v68+. In practice, it runs into an LLVM
assertion when using a `freeze` instruction on `f16` values, similar to the
issue we had for LoongArch.
---
 src/codegen/llvm.zig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig
index 2cd1af783e..52b1960048 100644
--- a/src/codegen/llvm.zig
+++ b/src/codegen/llvm.zig
@@ -12380,6 +12380,7 @@ fn backendSupportsF80(target: std.Target) bool {
 /// if it produces miscompilations.
 fn backendSupportsF16(target: std.Target) bool {
     return switch (target.cpu.arch) {
+        .hexagon,
         .powerpc,
         .powerpcle,
         .powerpc64,