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Disable llvm.prefetch for PowerPC
This instruction is not supported on this backend, so should just be a noop.
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@ -9168,7 +9168,13 @@ pub const FuncGen = struct {
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const target = self.dg.module.getTarget();
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switch (prefetch.cache) {
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.instruction => switch (target.cpu.arch) {
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.x86_64, .i386 => return null,
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.x86_64,
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.i386,
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.powerpc,
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.powerpcle,
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.powerpc64,
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.powerpc64le,
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=> return null,
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.arm, .armeb, .thumb, .thumbeb => {
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switch (prefetch.rw) {
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.write => return null,
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@ -6742,6 +6742,10 @@ static LLVMValueRef ir_render_prefetch(CodeGen *g, Stage1Air *executable, Stage1
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switch (g->zig_target->arch) {
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case ZigLLVM_x86:
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case ZigLLVM_x86_64:
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case ZigLLVM_ppc:
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case ZigLLVM_ppcle:
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case ZigLLVM_ppc64:
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case ZigLLVM_ppc64le:
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return nullptr;
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default:
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break;
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