diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig
index 2189bb3127..40953182d9 100644
--- a/src/codegen/llvm.zig
+++ b/src/codegen/llvm.zig
@@ -9168,7 +9168,13 @@ pub const FuncGen = struct {
         const target = self.dg.module.getTarget();
         switch (prefetch.cache) {
             .instruction => switch (target.cpu.arch) {
-                .x86_64, .i386 => return null,
+                .x86_64,
+                .i386,
+                .powerpc,
+                .powerpcle,
+                .powerpc64,
+                .powerpc64le,
+                => return null,
                 .arm, .armeb, .thumb, .thumbeb => {
                     switch (prefetch.rw) {
                         .write => return null,
diff --git a/src/stage1/codegen.cpp b/src/stage1/codegen.cpp
index 5546605b88..48f9d20ec4 100644
--- a/src/stage1/codegen.cpp
+++ b/src/stage1/codegen.cpp
@@ -6742,6 +6742,10 @@ static LLVMValueRef ir_render_prefetch(CodeGen *g, Stage1Air *executable, Stage1
         switch (g->zig_target->arch) {
             case ZigLLVM_x86:
             case ZigLLVM_x86_64:
+            case ZigLLVM_ppc:
+            case ZigLLVM_ppcle:
+            case ZigLLVM_ppc64:
+            case ZigLLVM_ppc64le:
                 return nullptr;
             default:
                 break;