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stage2: add compile errors for comptime @shrExact and @divExact failures
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12
src/Sema.zig
12
src/Sema.zig
@ -10441,7 +10441,7 @@ fn zirShr(
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// Detect if any ones would be shifted out.
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const truncated = try lhs_val.intTruncBitsAsValue(lhs_ty, sema.arena, .unsigned, rhs_val, target);
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if (!(try truncated.compareWithZeroAdvanced(.eq, sema.kit(block, src)))) {
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return sema.addConstUndef(lhs_ty);
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return sema.fail(block, src, "exact shift shifted out 1 bits", .{});
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}
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}
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const val = try lhs_val.shr(rhs_val, lhs_ty, sema.arena, target);
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@ -11346,13 +11346,19 @@ fn zirDivExact(sema: *Sema, block: *Block, inst: Zir.Inst.Index) CompileError!Ai
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if (maybe_lhs_val) |lhs_val| {
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if (maybe_rhs_val) |rhs_val| {
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if (is_int) {
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// TODO: emit compile error if there is a remainder
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const modulus_val = try lhs_val.intMod(rhs_val, resolved_type, sema.arena, target);
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if (modulus_val.compareWithZero(.neq)) {
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return sema.fail(block, src, "exact division produced remainder", .{});
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}
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return sema.addConstant(
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resolved_type,
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try lhs_val.intDiv(rhs_val, resolved_type, sema.arena, target),
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);
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} else {
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// TODO: emit compile error if there is a remainder
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const modulus_val = try lhs_val.floatMod(rhs_val, resolved_type, sema.arena, target);
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if (modulus_val.compareWithZero(.neq)) {
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return sema.fail(block, src, "exact division produced remainder", .{});
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}
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return sema.addConstant(
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resolved_type,
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try lhs_val.floatDiv(rhs_val, resolved_type, sema.arena, target),
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10
test/cases/compile_errors/exact division failure.zig
Normal file
10
test/cases/compile_errors/exact division failure.zig
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@ -0,0 +1,10 @@
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comptime {
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const x = @divExact(10, 3);
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_ = x;
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}
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// error
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// backend=llvm
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// target=native
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//
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// :2:15: error: exact division produced remainder
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10
test/cases/compile_errors/float exact division failure.zig
Normal file
10
test/cases/compile_errors/float exact division failure.zig
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@ -0,0 +1,10 @@
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comptime {
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const x = @divExact(10.0, 3.0);
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_ = x;
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}
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// error
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// backend=llvm
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// target=native
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//
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// :2:15: error: exact division produced remainder
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@ -4,7 +4,7 @@ comptime {
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}
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// error
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// backend=stage1
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// backend=llvm
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// target=native
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//
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// tmp.zig:2:15: error: exact shift shifted out 1 bits
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// :2:15: error: exact shift shifted out 1 bits
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