From cb901e578cbc321003d5e4327d51d349d91f6dd6 Mon Sep 17 00:00:00 2001 From: LeRoyce Pearson Date: Mon, 15 Aug 2022 02:28:42 -0600 Subject: [PATCH] stage2: add compile errors for comptime `@shrExact` and `@divExact` failures --- src/Sema.zig | 12 +++++++++--- test/cases/compile_errors/exact division failure.zig | 10 ++++++++++ .../compile_errors/float exact division failure.zig | 10 ++++++++++ .../{stage1/obj => }/shrExact_shifts_out_1_bits.zig | 4 ++-- 4 files changed, 31 insertions(+), 5 deletions(-) create mode 100644 test/cases/compile_errors/exact division failure.zig create mode 100644 test/cases/compile_errors/float exact division failure.zig rename test/cases/compile_errors/{stage1/obj => }/shrExact_shifts_out_1_bits.zig (58%) diff --git a/src/Sema.zig b/src/Sema.zig index d697ab0a99..12851cc9ad 100644 --- a/src/Sema.zig +++ b/src/Sema.zig @@ -10441,7 +10441,7 @@ fn zirShr( // Detect if any ones would be shifted out. const truncated = try lhs_val.intTruncBitsAsValue(lhs_ty, sema.arena, .unsigned, rhs_val, target); if (!(try truncated.compareWithZeroAdvanced(.eq, sema.kit(block, src)))) { - return sema.addConstUndef(lhs_ty); + return sema.fail(block, src, "exact shift shifted out 1 bits", .{}); } } const val = try lhs_val.shr(rhs_val, lhs_ty, sema.arena, target); @@ -11346,13 +11346,19 @@ fn zirDivExact(sema: *Sema, block: *Block, inst: Zir.Inst.Index) CompileError!Ai if (maybe_lhs_val) |lhs_val| { if (maybe_rhs_val) |rhs_val| { if (is_int) { - // TODO: emit compile error if there is a remainder + const modulus_val = try lhs_val.intMod(rhs_val, resolved_type, sema.arena, target); + if (modulus_val.compareWithZero(.neq)) { + return sema.fail(block, src, "exact division produced remainder", .{}); + } return sema.addConstant( resolved_type, try lhs_val.intDiv(rhs_val, resolved_type, sema.arena, target), ); } else { - // TODO: emit compile error if there is a remainder + const modulus_val = try lhs_val.floatMod(rhs_val, resolved_type, sema.arena, target); + if (modulus_val.compareWithZero(.neq)) { + return sema.fail(block, src, "exact division produced remainder", .{}); + } return sema.addConstant( resolved_type, try lhs_val.floatDiv(rhs_val, resolved_type, sema.arena, target), diff --git a/test/cases/compile_errors/exact division failure.zig b/test/cases/compile_errors/exact division failure.zig new file mode 100644 index 0000000000..d134e0e2fb --- /dev/null +++ b/test/cases/compile_errors/exact division failure.zig @@ -0,0 +1,10 @@ +comptime { + const x = @divExact(10, 3); + _ = x; +} + +// error +// backend=llvm +// target=native +// +// :2:15: error: exact division produced remainder diff --git a/test/cases/compile_errors/float exact division failure.zig b/test/cases/compile_errors/float exact division failure.zig new file mode 100644 index 0000000000..c09defc56e --- /dev/null +++ b/test/cases/compile_errors/float exact division failure.zig @@ -0,0 +1,10 @@ +comptime { + const x = @divExact(10.0, 3.0); + _ = x; +} + +// error +// backend=llvm +// target=native +// +// :2:15: error: exact division produced remainder diff --git a/test/cases/compile_errors/stage1/obj/shrExact_shifts_out_1_bits.zig b/test/cases/compile_errors/shrExact_shifts_out_1_bits.zig similarity index 58% rename from test/cases/compile_errors/stage1/obj/shrExact_shifts_out_1_bits.zig rename to test/cases/compile_errors/shrExact_shifts_out_1_bits.zig index 223db76630..dd23c4bcb3 100644 --- a/test/cases/compile_errors/stage1/obj/shrExact_shifts_out_1_bits.zig +++ b/test/cases/compile_errors/shrExact_shifts_out_1_bits.zig @@ -4,7 +4,7 @@ comptime { } // error -// backend=stage1 +// backend=llvm // target=native // -// tmp.zig:2:15: error: exact shift shifted out 1 bits +// :2:15: error: exact shift shifted out 1 bits