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std.debug: add CPU context and DWARF mappings for m68k

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Alex Rønne Petersen 2025-10-16 17:09:30 +02:00
parent eb36a45ed9
commit ba9ab3fb67
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3 changed files with 49 additions and 3 deletions
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3
lib/std/debug/Dwarf.zig
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@ -1435,6 +1435,7 @@ pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {
.hexagon => 76,
.lanai => 2,
.loongarch32, .loongarch64 => 64,
.m68k => 26,
.mips, .mipsel, .mips64, .mips64el => 66,
.or1k => 35,
.powerpc, .powerpcle, .powerpc64, .powerpc64le => 67,
@ -1456,6 +1457,7 @@ pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 {
.hexagon => 30,
.lanai => 5,
.loongarch32, .loongarch64 => 22,
.m68k => 14,
.mips, .mipsel, .mips64, .mips64el => 30,
.or1k => 2,
.powerpc, .powerpcle, .powerpc64, .powerpc64le => 1,
@ -1477,6 +1479,7 @@ pub fn spRegNum(arch: std.Target.Cpu.Arch) u16 {
.hexagon => 29,
.lanai => 4,
.loongarch32, .loongarch64 => 3,
.m68k => 15,
.mips, .mipsel, .mips64, .mips64el => 29,
.or1k => 1,
.powerpc, .powerpcle, .powerpc64, .powerpc64le => 1,

9
lib/std/debug/SelfInfo/Elf.zig
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@ -94,19 +94,21 @@ pub const can_unwind: bool = s: {
// Notably, we are yet to support unwinding on ARM. There, unwinding is not done through
// `.eh_frame`, but instead with the `.ARM.exidx` section, which has a different format.
const archs: []const std.Target.Cpu.Arch = switch (builtin.target.os.tag) {
// Not supported yet: arm, m68k
// Not supported yet: arm
.haiku => &.{
.aarch64,
.m68k,
.riscv64,
.x86,
.x86_64,
},
// Not supported yet: arc, arm/armeb/thumb/thumbeb, m68k, xtensa
// Not supported yet: arc, arm/armeb/thumb/thumbeb, xtensa
.linux => &.{
.aarch64,
.aarch64_be,
.csky,
.loongarch64,
.m68k,
.mips,
.mipsel,
.mips64,
@ -133,10 +135,11 @@ pub const can_unwind: bool = s: {
.riscv64,
.x86_64,
},
// Not supported yet: arm/armeb, m68k, mips64/mips64el
// Not supported yet: arm/armeb, mips64/mips64el
.netbsd => &.{
.aarch64,
.aarch64_be,
.m68k,
.mips,
.mipsel,
.x86,

40
lib/std/debug/cpu_context.zig
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@ -10,6 +10,7 @@ else switch (native_arch) {
.hexagon => Hexagon,
.lanai => Lanai,
.loongarch32, .loongarch64 => LoongArch,
.m68k => M68k,
.mips, .mipsel, .mips64, .mips64el => Mips,
.or1k => Or1k,
.powerpc, .powerpcle, .powerpc64, .powerpc64le => Powerpc,
@ -87,6 +88,11 @@ pub fn fromPosixSignalContext(ctx_ptr: ?*const anyopaque) ?Native {
.r = uc.mcontext.r,
.pc = uc.mcontext.pc,
},
.m68k => .{
.d = uc.mcontext.d,
.a = uc.mcontext.a,
.pc = uc.mcontext.pc,
},
.powerpc, .powerpcle, .powerpc64, .powerpc64le => .{
.r = uc.mcontext.r,
.pc = uc.mcontext.pc,
@ -697,6 +703,40 @@ const LoongArch = extern struct {
}
};
/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
const M68k = extern struct {
/// The numbered data registers d0 - d7.
d: [8]u32,
/// The numbered address registers a0 - a7.
a: [8]u32,
pc: u32,
pub inline fn current() M68k {
var ctx: M68k = undefined;
asm volatile (
\\ movem.l %%d0 - %%a7, (%%a0)
\\ lea.l (%%pc), %%a1
\\ move.l %%a1, (%%a0, 64)
:
: [ctx] "{a0}" (&ctx),
: .{ .a1 = true, .memory = true });
return ctx;
}
pub fn dwarfRegisterBytes(ctx: *M68k, register_num: u16) DwarfRegisterError![]u8 {
switch (register_num) {
0...7 => return @ptrCast(&ctx.d[register_num]),
8...15 => return @ptrCast(&ctx.a[register_num - 8]),
26 => return @ptrCast(&ctx.pc),
16...23 => return error.UnsupportedRegister, // fp0 - fp7
24...25 => return error.UnsupportedRegister, // Return columns in GCC...?
else => return error.InvalidRegister,
}
}
};
/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
const Mips = extern struct {
/// The numbered general-purpose registers r0 - r31. r0 must be zero.