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std.debug: add CPU context and DWARF mappings for or1k

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Alex Rønne Petersen 2025-10-16 15:56:32 +02:00
parent de3947608c
commit eb36a45ed9
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3 changed files with 66 additions and 1 deletions
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3
lib/std/debug/Dwarf.zig
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@ -1436,6 +1436,7 @@ pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {
.lanai => 2,
.loongarch32, .loongarch64 => 64,
.mips, .mipsel, .mips64, .mips64el => 66,
.or1k => 35,
.powerpc, .powerpcle, .powerpc64, .powerpc64le => 67,
.riscv32, .riscv32be, .riscv64, .riscv64be => 65,
.s390x => 65,
@ -1456,6 +1457,7 @@ pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 {
.lanai => 5,
.loongarch32, .loongarch64 => 22,
.mips, .mipsel, .mips64, .mips64el => 30,
.or1k => 2,
.powerpc, .powerpcle, .powerpc64, .powerpc64le => 1,
.riscv32, .riscv32be, .riscv64, .riscv64be => 8,
.s390x => 11,
@ -1476,6 +1478,7 @@ pub fn spRegNum(arch: std.Target.Cpu.Arch) u16 {
.lanai => 4,
.loongarch32, .loongarch64 => 3,
.mips, .mipsel, .mips64, .mips64el => 29,
.or1k => 1,
.powerpc, .powerpcle, .powerpc64, .powerpc64le => 1,
.riscv32, .riscv32be, .riscv64, .riscv64be => 2,
.s390x => 15,

3
lib/std/debug/SelfInfo/Elf.zig
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@ -101,7 +101,7 @@ pub const can_unwind: bool = s: {
.x86,
.x86_64,
},
// Not supported yet: arc, arm/armeb/thumb/thumbeb, m68k, or1k, xtensa
// Not supported yet: arc, arm/armeb/thumb/thumbeb, m68k, xtensa
.linux => &.{
.aarch64,
.aarch64_be,
@ -111,6 +111,7 @@ pub const can_unwind: bool = s: {
.mipsel,
.mips64,
.mips64el,
.or1k,
.riscv32,
.riscv64,
.s390x,

61
lib/std/debug/cpu_context.zig
View File

@ -11,6 +11,7 @@ else switch (native_arch) {
.lanai => Lanai,
.loongarch32, .loongarch64 => LoongArch,
.mips, .mipsel, .mips64, .mips64el => Mips,
.or1k => Or1k,
.powerpc, .powerpcle, .powerpc64, .powerpc64le => Powerpc,
.sparc, .sparc64 => Sparc,
.riscv32, .riscv32be, .riscv64, .riscv64be => Riscv,
@ -818,6 +819,66 @@ const Mips = extern struct {
}
};
/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
const Or1k = extern struct {
/// The numbered general-purpose registers r0 - r31.
r: [32]u32,
pc: u32,
pub inline fn current() Or1k {
var ctx: Or1k = undefined;
asm volatile (
\\ l.sw 0(r15), r0
\\ l.sw 4(r15), r1
\\ l.sw 8(r15), r2
\\ l.sw 12(r15), r3
\\ l.sw 16(r15), r4
\\ l.sw 20(r15), r5
\\ l.sw 24(r15), r6
\\ l.sw 28(r15), r7
\\ l.sw 32(r15), r8
\\ l.sw 36(r15), r9
\\ l.sw 40(r15), r10
\\ l.sw 44(r15), r11
\\ l.sw 48(r15), r12
\\ l.sw 52(r15), r13
\\ l.sw 56(r15), r14
\\ l.sw 60(r15), r15
\\ l.sw 64(r15), r16
\\ l.sw 68(r15), r17
\\ l.sw 72(r15), r18
\\ l.sw 76(r15), r19
\\ l.sw 80(r15), r20
\\ l.sw 84(r15), r21
\\ l.sw 88(r15), r22
\\ l.sw 92(r15), r23
\\ l.sw 96(r15), r24
\\ l.sw 100(r15), r25
\\ l.sw 104(r15), r26
\\ l.sw 108(r15), r27
\\ l.sw 112(r15), r28
\\ l.sw 116(r15), r29
\\ l.sw 120(r15), r30
\\ l.sw 124(r15), r31
\\ l.jal 1f
\\1:
\\ l.sw 128(r15), r9
:
: [ctx] "{r15}" (&ctx),
: .{ .r9 = true, .memory = true });
return ctx;
}
pub fn dwarfRegisterBytes(ctx: *Or1k, register_num: u16) DwarfRegisterError![]u8 {
switch (register_num) {
0...31 => return @ptrCast(&ctx.r[register_num]),
35 => return @ptrCast(&ctx.pc),
else => return error.InvalidRegister,
}
}
};
/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
const Powerpc = extern struct {
/// The numbered general-purpose registers r0 - r31.