mirror of
https://github.com/ziglang/zig.git
synced 2026-02-13 12:59:04 +00:00
compiler: Explicitly specify loongarch ABI when talking to LLVM.
Necessary because of: dc665fa5f5
This commit is contained in:
parent
673544b783
commit
b95081209a
@ -500,33 +500,42 @@ pub fn llvmMachineAbi(target: std.Target) ?[:0]const u8 {
|
||||
// Once our self-hosted linker can handle both ABIs, this hack should go away.
|
||||
if (target.cpu.arch == .powerpc64) return "elfv2";
|
||||
|
||||
switch (target.cpu.arch) {
|
||||
.riscv64 => {
|
||||
const featureSetHas = std.Target.riscv.featureSetHas;
|
||||
if (featureSetHas(target.cpu.features, .e)) {
|
||||
return "lp64e";
|
||||
} else if (featureSetHas(target.cpu.features, .d)) {
|
||||
return "lp64d";
|
||||
} else if (featureSetHas(target.cpu.features, .f)) {
|
||||
return "lp64f";
|
||||
} else {
|
||||
return "lp64";
|
||||
}
|
||||
return switch (target.cpu.arch) {
|
||||
// TODO: `muslsf` and `muslf32` in LLVM 20.
|
||||
.loongarch64 => switch (target.abi) {
|
||||
.gnusf => "lp64s",
|
||||
.gnuf32 => "lp64f",
|
||||
else => "lp64d",
|
||||
},
|
||||
.riscv32 => {
|
||||
const featureSetHas = std.Target.riscv.featureSetHas;
|
||||
if (featureSetHas(target.cpu.features, .e)) {
|
||||
return "ilp32e";
|
||||
} else if (featureSetHas(target.cpu.features, .d)) {
|
||||
return "ilp32d";
|
||||
} else if (featureSetHas(target.cpu.features, .f)) {
|
||||
return "ilp32f";
|
||||
} else {
|
||||
return "ilp32";
|
||||
}
|
||||
.loongarch32 => switch (target.abi) {
|
||||
.gnusf => "ilp32s",
|
||||
.gnuf32 => "ilp32f",
|
||||
else => "ilp32d",
|
||||
},
|
||||
else => return null,
|
||||
}
|
||||
.riscv64 => b: {
|
||||
const featureSetHas = std.Target.riscv.featureSetHas;
|
||||
break :b if (featureSetHas(target.cpu.features, .e))
|
||||
"lp64e"
|
||||
else if (featureSetHas(target.cpu.features, .d))
|
||||
"lp64d"
|
||||
else if (featureSetHas(target.cpu.features, .f))
|
||||
"lp64f"
|
||||
else
|
||||
"lp64";
|
||||
},
|
||||
.riscv32 => b: {
|
||||
const featureSetHas = std.Target.riscv.featureSetHas;
|
||||
break :b if (featureSetHas(target.cpu.features, .e))
|
||||
"ilp32e"
|
||||
else if (featureSetHas(target.cpu.features, .d))
|
||||
"ilp32d"
|
||||
else if (featureSetHas(target.cpu.features, .f))
|
||||
"ilp32f"
|
||||
else
|
||||
"ilp32";
|
||||
},
|
||||
else => null,
|
||||
};
|
||||
}
|
||||
|
||||
/// This function returns 1 if function alignment is not observable or settable. Note that this
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user