From b95081209a83be39b52b3f304387f75cfab22e9e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Fri, 24 Jan 2025 04:01:18 +0100 Subject: [PATCH] compiler: Explicitly specify loongarch ABI when talking to LLVM. Necessary because of: https://github.com/llvm/llvm-project/commit/dc665fa5f5b8b572479ceac6bf32e0174de65f1e --- src/target.zig | 59 +++++++++++++++++++++++++++++--------------------- 1 file changed, 34 insertions(+), 25 deletions(-) diff --git a/src/target.zig b/src/target.zig index 99e0fd1faa..b7e1c73ef1 100644 --- a/src/target.zig +++ b/src/target.zig @@ -500,33 +500,42 @@ pub fn llvmMachineAbi(target: std.Target) ?[:0]const u8 { // Once our self-hosted linker can handle both ABIs, this hack should go away. if (target.cpu.arch == .powerpc64) return "elfv2"; - switch (target.cpu.arch) { - .riscv64 => { - const featureSetHas = std.Target.riscv.featureSetHas; - if (featureSetHas(target.cpu.features, .e)) { - return "lp64e"; - } else if (featureSetHas(target.cpu.features, .d)) { - return "lp64d"; - } else if (featureSetHas(target.cpu.features, .f)) { - return "lp64f"; - } else { - return "lp64"; - } + return switch (target.cpu.arch) { + // TODO: `muslsf` and `muslf32` in LLVM 20. + .loongarch64 => switch (target.abi) { + .gnusf => "lp64s", + .gnuf32 => "lp64f", + else => "lp64d", }, - .riscv32 => { - const featureSetHas = std.Target.riscv.featureSetHas; - if (featureSetHas(target.cpu.features, .e)) { - return "ilp32e"; - } else if (featureSetHas(target.cpu.features, .d)) { - return "ilp32d"; - } else if (featureSetHas(target.cpu.features, .f)) { - return "ilp32f"; - } else { - return "ilp32"; - } + .loongarch32 => switch (target.abi) { + .gnusf => "ilp32s", + .gnuf32 => "ilp32f", + else => "ilp32d", }, - else => return null, - } + .riscv64 => b: { + const featureSetHas = std.Target.riscv.featureSetHas; + break :b if (featureSetHas(target.cpu.features, .e)) + "lp64e" + else if (featureSetHas(target.cpu.features, .d)) + "lp64d" + else if (featureSetHas(target.cpu.features, .f)) + "lp64f" + else + "lp64"; + }, + .riscv32 => b: { + const featureSetHas = std.Target.riscv.featureSetHas; + break :b if (featureSetHas(target.cpu.features, .e)) + "ilp32e" + else if (featureSetHas(target.cpu.features, .d)) + "ilp32d" + else if (featureSetHas(target.cpu.features, .f)) + "ilp32f" + else + "ilp32"; + }, + else => null, + }; } /// This function returns 1 if function alignment is not observable or settable. Note that this