mirror/zig
1
0
Fork 0
mirror of https://github.com/ziglang/zig.git synced 2025-12-30 18:13:19 +00:00
Code Issues Packages Projects Releases Wiki Activity

stage2: sparcv9: Simplify genLoad/genStore

Browse Source
This commit is contained in:
Koakuma 2022-04-21 06:06:58 +07:00 committed by Jakub Konka
parent f6bf3dd78c
commit ae201807f5
1 changed files with 20 additions and 82 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

102
src/arch/sparcv9/CodeGen.zig
View File

@ -1185,48 +1185,17 @@ fn genLoad(self: *Self, value_reg: Register, addr_reg: Register, comptime off_ty
const rs2_or_imm = if (is_imm) .{ .imm = off } else .{ .rs2 = off };
switch (abi_size) {
1 => {
1, 2, 4, 8 => {
const tag: Mir.Inst.Tag = switch (abi_size) {
1 => .ldub,
2 => .lduh,
4 => .lduw,
8 => .ldx,
else => unreachable, // unexpected abi size
};
_ = try self.addInst(.{
.tag = .ldub,
.data = .{
.arithmetic_3op = .{
.is_imm = is_imm,
.rd = value_reg,
.rs1 = addr_reg,
.rs2_or_imm = rs2_or_imm,
},
},
});
},
2 => {
_ = try self.addInst(.{
.tag = .lduh,
.data = .{
.arithmetic_3op = .{
.is_imm = is_imm,
.rd = value_reg,
.rs1 = addr_reg,
.rs2_or_imm = rs2_or_imm,
},
},
});
},
4 => {
_ = try self.addInst(.{
.tag = .lduw,
.data = .{
.arithmetic_3op = .{
.is_imm = is_imm,
.rd = value_reg,
.rs1 = addr_reg,
.rs2_or_imm = rs2_or_imm,
},
},
});
},
8 => {
_ = try self.addInst(.{
.tag = .ldx,
.tag = tag,
.data = .{
.arithmetic_3op = .{
.is_imm = is_imm,
@ -1436,48 +1405,17 @@ fn genStore(self: *Self, value_reg: Register, addr_reg: Register, comptime off_t
const rs2_or_imm = if (is_imm) .{ .imm = off } else .{ .rs2 = off };
switch (abi_size) {
1 => {
1, 2, 4, 8 => {
const tag: Mir.Inst.Tag = switch (abi_size) {
1 => .stb,
2 => .sth,
4 => .stw,
8 => .stx,
else => unreachable, // unexpected abi size
};
_ = try self.addInst(.{
.tag = .stb,
.data = .{
.arithmetic_3op = .{
.is_imm = is_imm,
.rd = value_reg,
.rs1 = addr_reg,
.rs2_or_imm = rs2_or_imm,
},
},
});
},
2 => {
_ = try self.addInst(.{
.tag = .sth,
.data = .{
.arithmetic_3op = .{
.is_imm = is_imm,
.rd = value_reg,
.rs1 = addr_reg,
.rs2_or_imm = rs2_or_imm,
},
},
});
},
4 => {
_ = try self.addInst(.{
.tag = .stw,
.data = .{
.arithmetic_3op = .{
.is_imm = is_imm,
.rd = value_reg,
.rs1 = addr_reg,
.rs2_or_imm = rs2_or_imm,
},
},
});
},
8 => {
_ = try self.addInst(.{
.tag = .stx,
.tag = tag,
.data = .{
.arithmetic_3op = .{
.is_imm = is_imm,